Abstract: A circuit is disclosed that can output signals from different circuit blocks at a common output terminal with a smaller number of transistors than conventional approaches. When a level shifter circuit receives a high voltage level at a control terminal (2), a level shifter unit (12) is placed in the operational state to provide an output signal from a low voltage system block, and a clocked inverter (106) is placed in the non-operational state. When a level shifter circuit receives a low voltage level at a control terminal (2), a clocked inverter (106) is placed in the operational state to provide an output signal from a high voltage system block. At the same time, PMOS transistor (105) can be turned on, resulting in PMOS transistors (5) being turned off. Further, NMOS transistors (109 and 110) are turned off. This can result in an output impedance of a level shifter unit (12) being set to a high impedance state.

Abstract: A circuit is disclosed that can output signals from different circuit blocks at a common output terminal with a smaller number of transistors than conventional approaches. When a level shifter circuit receives a high voltage level at a control terminal (2), a level shifter unit (12) is placed in the operational state to provide an output signal from a low voltage system block, and a clocked inverter (106) is placed in the non-operational state. When a level shifter circuit receives a low voltage level at a control terminal (2), a clocked inverter (106) is placed in the operational state to provide an output signal from a high voltage system block. At the same time, PMOS transistor (105) can be turned on, resulting in PMOS transistors (5) being turned off. Further, NMOS transistors (109 and 110) are turned off. This can result in an output impedance of a level shifter unit (12) being set to a high impedance state.