Patents by Inventor Kazuo Umeda
Kazuo Umeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8592686Abstract: A method for manufacturing a printed circuit board assembled panel by a simple process with an excellent material yield and a high conforming product rate. Unit printed circuit boards previously manufactured are arranged in a frame in a prescribed relationship. Then, the printed circuit boards are fixed to one another, and the printed circuit board and the frame body are fixed to one another.Type: GrantFiled: April 4, 2005Date of Patent: November 26, 2013Assignee: Dai Nippon Printing Co., Ltd.Inventors: Atsushi Kobayashi, Kazuo Umeda, Wataru Gotou, Takahiro Sahara, Susumu Nakazawa, Kiyoshi Takeuchi, Takayuki Terauchi
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Patent number: 7815441Abstract: A rigid-flexible board and a method for manufacturing the same can be provided, whereby the material yield ratio can be enhanced and the productive yield can be also enhanced. A rigid board with a step for connection and a flexible board with a connector at the edge thereof are formed independently. Then, the connecting area is spot facing processed so that the depth of the thus obtained depressed portion is equal to or lower than the thickness of the flexible board. The connector of the flexible board is electrically connected to the vertical wiring area of the depressed portion.Type: GrantFiled: April 4, 2005Date of Patent: October 19, 2010Assignee: Dai Nippon Printing Co., Ltd.Inventors: Atsushi Kobayashi, Kazuo Umeda, Wataru Gotou, Susumu Nakazawa, Kiyoshi Takeuchi, Takayuki Terauchi
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Patent number: 7678450Abstract: To provide a sewing thread that is excellent in high-speed sewability and automatic sewing characteristics. A sewing thread includes a plurality of under-twisted yarns provided with upper-twist, the yarns each being composed of a sheath-core structure yarn composed of two or more multifilament yarns, wherein part of the sheath-core structure yarn protrudes as loops on a yarn surface, the loops being composed of 50 to 300 loops/m with 0.7 to less than 1.2 mm length and 10 or less loops/m with 1.2 mm or more length, and wherein the yarns have a strength of 4 to 6 CN/dtex.Type: GrantFiled: April 3, 2003Date of Patent: March 16, 2010Assignee: Toray Industries, Inc.Inventors: Haruki Kitamura, Toshihiko Kimura, Kazuo Umeda, Yoshikazu Tsuji, Naoki Yamaga, Akihiro Maekawa
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Patent number: 7550344Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.Type: GrantFiled: August 10, 2007Date of Patent: June 23, 2009Assignee: Panasonic CorporationInventors: Toyoji Ito, Eiji Fujii, Kazuo Umeda
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Publication number: 20090014205Abstract: A method for manufacturing a printed circuit board assembled panel by a simple process with an excellent material yield and a high conforming product rate. Unit printed circuit boards previously manufactured are arranged in a frame in a prescribed relationship. Then, the printed circuit boards are fixed to one another, and the printed circuit board and the frame body are fixed to one another.Type: ApplicationFiled: April 4, 2005Publication date: January 15, 2009Inventors: Atsushi Kobayashi, Kazuo Umeda, Wataru Gotou, Takahiro Sahara, Susumu Nakazawa, Kiyoshi Takeuchi, Takayuki Terauchi
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Publication number: 20070293007Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.Type: ApplicationFiled: August 10, 2007Publication date: December 20, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toyoji Ito, Eiji Fujii, Kazuo Umeda
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Publication number: 20070281505Abstract: A rigid-flexible board and a method for manufacturing the same can be provided, whereby the material yield ratio can be enhanced and the productive yield can be also enhanced. A rigid board with a step for connection and a flexible board with a connector at the edge thereof are formed independently. Then, the connecting area is spot facing processed so that the depth of the thus obtained depressed portion is equal to or lower than the thickness of the flexible board. The connector of the flexible board is electrically connected to the vertical wiring area of the depressed portion.Type: ApplicationFiled: April 4, 2005Publication date: December 6, 2007Inventors: Atsushi Kobayashi, Kazuo Umeda, Wataru Gotou, Susumu Nakazawa, Kiyoshi Takeuchi, Takayuki Terauchi
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Patent number: 7288456Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.Type: GrantFiled: June 29, 2005Date of Patent: October 30, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoji Ito, Eiji Fujii, Kazuo Umeda
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Patent number: 6995092Abstract: When an electronic device having an element including an insulating metal oxide film is manufactured, either dry cleaning or a cleaning solution containing substantially no water is used in a cleaning step conducted after a step of forming the insulating metal oxide film.Type: GrantFiled: October 2, 2002Date of Patent: February 7, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kazuo Umeda
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Publication number: 20050239251Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.Type: ApplicationFiled: June 29, 2005Publication date: October 27, 2005Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toyoji Ito, Eiji Fujii, Kazuo Umeda
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Publication number: 20050202240Abstract: To provide a sewing thread that is excellent in high-speed sewability and automatic sewing characteristics. A sewing thread includes a plurality of under-twisted yarns provided with upper-twist, the yarns each being composed of a sheath-core structure yarn composed of two or more multifilament yarns, wherein part of the sheath-core structure yarn protrudes as loops on a yarn surface, the loops being composed of 50 to 300 loops/m with 0.7 to less than 1.2 mm length and 10 or less loops/m with 1.2 mm or more length, and wherein the yarns have a strength of 4 to 6 CN/dtex.Type: ApplicationFiled: April 3, 2003Publication date: September 15, 2005Applicant: TORAY Industries, Inc.Inventors: Haruki Kitamura, Toshihiko Kimura, Kazuo Umeda, Yoshikazu Tsuji, Naoki Yamaga, Akihiro Maekawa
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Patent number: 6943398Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.Type: GrantFiled: November 13, 2003Date of Patent: September 13, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toyoji Ito, Eiji Fujii, Kazuo Umeda
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Patent number: 6942817Abstract: A wireless suspension blank is made using a two-layer laminate composed of a metallic layer with the spring property and an electrically insulating layer. The first method includes a first step for working the metallic layer by the photo etching method, a second step for forming a wiring part on the insulating layer by the semi-additive method and a third step for working the insulating layer by the wet-etching method. The second method includes a first step for working the metallic layer by the photo etching method, a second step for forming a wiring part on the insulating layer by the semi-additive method and a third step for working the insulating layer by the plasma etching method. The third method includes a first step for forming a wiring part on the metallic layer by the semi-additive method, a second step for working the metallic layer by the wet-etching method and a third step for working the insulating layer by the dry-etching method or the wet-etching method.Type: GrantFiled: March 21, 2001Date of Patent: September 13, 2005Assignee: Dainippon Printing Co., Ltd.Inventors: Hiroshi Yagi, Shigeki Kawano, Kazuo Umeda, Jiro Takei, Yukio Iimura, Satoshi Sasaki, Katsuya Sakayori, Hiroko Amasaki
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Patent number: 6750148Abstract: A method of manufacturing a wireless suspension blank wherein three-layered laminate formed of a metallic layer having a spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used. The laminate used is a laminate in which an insulating layer is formed of a core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. The metallic layer and the conductive layer are processed by the photo etching method. The insulating layer is processed by the wet etching method.Type: GrantFiled: July 6, 2001Date of Patent: June 15, 2004Assignee: Dainippon Printing Co., Ltd.Inventors: Katsuya Sakayori, Shigeki Kawano, Hiroko Amasaki, Kazuo Umeda, Satoshi Sasaki, Hiroshi Yagi
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Publication number: 20040094791Abstract: A semiconductor device includes: a lower hydrogen-barrier film; a capacitor formed on the lower hydrogen-barrier film and including a lower electrode, a capacitive insulating film, and an upper electrode; an interlayer dielectric film formed so as to cover the periphery of the capacitor; and an upper hydrogen-barrier film covering the top and lateral portions of the capacitor. An opening, which exposes the lower hydrogen-barrier film where the lower hydrogen-barrier film is located around the capacitor, and which is tapered and flares upward, is formed in the interlayer dielectric film, and the upper hydrogen-barrier film is formed along the lateral and bottom faces of the opening, and is in contact with the lower hydrogen-barrier film in the opening.Type: ApplicationFiled: November 13, 2003Publication date: May 20, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Toyoji Ito, Eiji Fujii, Kazuo Umeda
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Patent number: 6730948Abstract: A semiconductor device includes at least a ferroelectric or high-dielectric-constant film and a surface coating that have been stacked in this order over a substrate. The surface coating is made of an acrylic resin.Type: GrantFiled: October 3, 2001Date of Patent: May 4, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuo Umeda, Keiichi Matsunaga
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Publication number: 20030064604Abstract: When an electronic device having an element including an insulating metal oxide film is manufactured, either dry cleaning or a cleaning solution containing substantially no water is used in a cleaning step conducted after a step of forming the insulating metal oxide film.Type: ApplicationFiled: October 2, 2002Publication date: April 3, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Kazuo Umeda
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Publication number: 20020167032Abstract: A semiconductor device includes at least a ferroelectric or high-dielectric-constant film and a surface coating that have been stacked in this order over a substrate. The surface coating is made of an acrylic resin.Type: ApplicationFiled: October 3, 2001Publication date: November 14, 2002Inventors: Kazuo Umeda, Keiichi Matsunaga
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Publication number: 20020027127Abstract: A wireless suspension blank is made using a two-layer laminate composed of a metallic layer with the spring property and an electrically insulating layer. The first method includes a first step for working the metallic layer by the photo etching method, a second step for forming a wiring part on the insulating layer by the semi-additive method and a third step for working the insulating layer by the wet-etching method. The second method includes a first step for working the metallic layer by the photo etching method, a second step for forming a wiring part on the insulating layer by the semi-additive method and a third step for working the insulating layer by the plasma etching method. The third method includes a first step for forming a wiring part on the metallic layer by the semi-additive method, a second step for working the metallic layer by the wet-etching method and a third step for working the insulating layer by the dry-etching method or the wet-etching method.Type: ApplicationFiled: March 21, 2001Publication date: March 7, 2002Inventors: Hiroshi Yagi, Shigeki Kawano, Kazuo Umeda, Jiro Takei, Yukio Iimura, Satoshi Sasaki, Katsuya Sakayori, Hiroko Amasaki
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Publication number: 20020003127Abstract: A method of manufacturing a wireless suspension blank is a method of manufacturing a wireless blank in which three-layered laminate formed of a metallic layer having the spring property and a conductive layer laminated on the metallic layer through an electrically insulating layer are used, wherein as the laminate used is a laminate in which an insulating layer is formed of core-insulating layer and adhesive layers laminated on both sides of the core-insulating layer, and the ratio of higher etching rate to lower etching rate of the respective layers of the insulating layer is between 6:1 and 1:1. By the photo etching method processed are the metallic layer and the conductive layer. The insulating layer is processed by the wet etching method.Type: ApplicationFiled: July 6, 2001Publication date: January 10, 2002Inventors: Katsuya Sakayori, Shigeki Kawano, Hiroko Amasaki, Kazuo Umeda, Satoshi Sasaki, Hiroshi Yagi