Patents by Inventor Kazurnari Hatade

Kazurnari Hatade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device
    Patent number: 7812402
    Abstract: In the upper surface of a p? substrate, an n-type impurity region is formed. In the upper surface of the n-type impurity region, a p-well is formed. Also in the upper surface of the n-type impurity region, a p+-type source region and a p+-type drain region are formed. In the upper surface of the p-well, an n+-type drain region and an n+-type source region are formed. In the p? substrate, an n+ buried layer having an impurity concentration higher than that of the n-type impurity region is formed. The n+ buried layer is formed in contact with the bottom surface of the n-type impurity region at a greater depth than the n-type impurity region.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 12, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kazurnari Hatade