Patents by Inventor Kazushi Fukuda
Kazushi Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7402473Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: GrantFiled: April 19, 2005Date of Patent: July 22, 2008Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Publication number: 20050196935Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: ApplicationFiled: April 19, 2005Publication date: September 8, 2005Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Patent number: 6881646Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: GrantFiled: March 21, 2003Date of Patent: April 19, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Publication number: 20030181020Abstract: A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: ApplicationFiled: March 21, 2003Publication date: September 25, 2003Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Publication number: 20030119276Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: ApplicationFiled: May 6, 2002Publication date: June 26, 2003Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Patent number: 6559027Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: GrantFiled: May 1, 2001Date of Patent: May 6, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Publication number: 20010026996Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: ApplicationFiled: May 1, 2001Publication date: October 4, 2001Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Patent number: 6242323Abstract: A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.Type: GrantFiled: August 16, 1999Date of Patent: June 5, 2001Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Norio Ishitsuka, Hideo Miura, Shuji Ikeda, Norio Suzuki, Yasushi Matsuda, Yasuko Yoshida, Hirohiko Yamamoto, Masamichi Kobayashi, Akira Takamatsu, Hirofumi Shimizu, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Patent number: 6057241Abstract: A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp<Tr.ltoreq.Type: GrantFiled: April 27, 1998Date of Patent: May 2, 2000Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yasushi Matsuda, Hideo Miura, Hirohiko Yamamoto, Masamichi Kobayashi, Shuji Ikeda, Akira Takamatsu, Norio Suzuki, Hirofumi Shimizu, Yasuko Yoshida, Kazushi Fukuda, Shinichi Horibe, Toshio Nozoe
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Patent number: 5880497Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.Type: GrantFiled: January 26, 1996Date of Patent: March 9, 1999Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Koichi Imato, Kazuo Yoshizaki, Kohji Yamasaki, Soichiro Hashiba, Keiichi Yoshizumi, Yasuko Yoshida, Kousuke Okuyama, Mitsugu Oshima, Kazushi Tomita, Tsuyoshi Tabata, Kazushi Fukuda, Junichi Takano, Toshiaki Yamanaka, Chiemi Hashimoto, Motoko Kawashima, Fumiyuki Kanai, Takashi Hashimoto
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Patent number: 5780328Abstract: When the source and drain regions (an n.sup.- type semiconductor region and an n.sup.+ type semiconductor region) of a complementary MISFET and a p-type semiconductor region for use as a punch-through stopper are formed in a p-type well in a substrate having a p- and an n-type well, p-type impurities for the punch-through stopper are suppressed from being supplied to the feeding portion (an n.sup.+ type semiconductor region) of the n-type well.Type: GrantFiled: April 7, 1997Date of Patent: July 14, 1998Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Co., Ltd.Inventors: Kazushi Fukuda, Yasuko Yoshida, Yutaka Hoshino, Naotaka Hashimoto, Kyoichiro Asayama, Yuuki Koide, Keiichi Yoshizumi, Eri Okamoto, Satoru Haga, Shuji Ikeda
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Patent number: 5508540Abstract: A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.Type: GrantFiled: February 2, 1994Date of Patent: April 16, 1996Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Koichi Imato, Kazuo Yoshizaki, Kohji Yamasaki, Soichiro Hashiba, Keiichi Yoshizumi, Yasuko Yoshida, Kousuke Okuyama, Mitsugu Oshima, Kazushi Tomita, Tsuyoshi Tabata, Kazushi Fukuda, Junichi Takano, Toshiaki Yamanaka, Chiemi Hashimoto, Motoko Kawashima, Fumiyuki Kanai, Takashi Hashimoto
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Patent number: 5444012Abstract: In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.Type: GrantFiled: July 20, 1994Date of Patent: August 22, 1995Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.Inventors: Keiichi Yoshizumi, Kazushi Fukuda, Seiichi Ariga, Shuji Ikeda, Makoto Saeki, Kiyoshi Nagai, Soichiro Hashiba, Shinji Nishihara, Fumiyuki Kanai
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Patent number: 5423664Abstract: A roller of a rotary type compressor is made of an iron base alloy essentially consisting of 2.0 to 3.9% carbon, 2.0 to 3.0% Si, 0.3 to 1.0% Mn, up to 0.10% S, more than zero and not more than 0.50% V, 0.3 to 1.0% P, 0.01 to 0.5% Sb, and balance of Fe and incidental impurities. Preferably, the iron base alloy further includes 0.001 to 0.5% B. This roller is suitable when hydrofluorocarbon is used as a refrigerant.Type: GrantFiled: July 15, 1994Date of Patent: June 13, 1995Assignee: Hitachi, Ltd.Inventors: Tadashi Iizuka, Kazushi Fukuda, Akihiko Ishiyama, Hideki Yazawa, Shoichi Nakashima, Hideki Nakamura
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Patent number: 5237148Abstract: A method for manufacturing a nozzle includes a step to change a spot diameter of a laser beam on a plate in which an orifice hole is formed. A device for manufacturing a nozzle includes a laser beam generating device for generating a laser beam, a work head comprising a lens to focus the laser beam on a plate, a driving device to move the work head upward and downward, a position detecting device for sending a signal indicating a position of the work head, and a controlling device for controlling an amount of the laser beam to be applied according to the signal from the position detecting device. The device for manufacturing a nozzle of the present invention changes the spot diameter of the laser beam on the plate. Therefore, the time period for forming an orifice hole in the nozzle can be shortened.Type: GrantFiled: October 3, 1991Date of Patent: August 17, 1993Assignee: Brother Kogyo KabushikiInventors: Hikoharu Aoki, Kazushi Fukuda
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Patent number: 5087181Abstract: A sliding structure such as a compressor and etc. comprising a member made of an iron base material and another member having a porous ceramic layer slidably contacted with the iron base member, wherein the surface portion of the iron base member has both a porous oxide film containing tri-iron tetroxide as a main constituent, and an oxynitride layer formed under the oxide film.Type: GrantFiled: March 6, 1990Date of Patent: February 11, 1992Assignee: Hitachi, Ltd.Inventors: Yasuo Kamitsuma, Isao Ishi, Yusaku Nakagawa, Noriyuki Ohnaka, Tadashi Iizuka, Kazushi Fukuda
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Patent number: 4944663Abstract: A sliding member of an iron-based non-porous material, such as vane, of a rotary compressor has a sliding surface processed by a surface treatment in which the surface is subjected to oxidizing and nitriding to form an oxidized and nitrided layer thereon. The surface is then subjected to a steam-treatment in which water is caused to react with components of the oxidized and nitrided layer to form a layer of oxidized iron of a porous network structure disposed outwardly of the oxidized and nitrided layer. The oxidized iron layer is composed mainly of tri-iron tetroxide and softer than the oxidized and nitrided layer.Type: GrantFiled: April 19, 1989Date of Patent: July 31, 1990Assignee: Hitachi, Ltd.Inventors: Tadashi Iizuka, Kazushi Fukuda, Shin Ishihara, Yasuo Kamitsuma, Yusaku Nakagawa