Patents by Inventor Kazushi Higashi

Kazushi Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8240539
    Abstract: The joining apparatus includes a suction nozzle for holding an electronic component, a board stage for holding a circuit board in opposition to the electronic component, and an excimer ultraviolet lamp placed at an irradiation position between the positioned electronic component and circuit board. In such a joining apparatus, ultraviolet irradiation to Au bumps of the electronic component and ultraviolet irradiation to board electrodes of the circuit board are performed concurrently by the excimer ultraviolet lamp to execute a cleaning process of the two metallic portions. Thereafter, ultrasonic vibrations are imparted to the two metallic portions while those metallic portions are kept in contact with each other, by which metal joining between the two metallic portions is fulfilled.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: August 14, 2012
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Tatsuo Sasaoka, Shinji Ishitani
  • Patent number: 8129739
    Abstract: In a semiconductor light emitting device having a matrix of a plurality of bumps composed of one n-bump formed on an n-electrode layer and of a large number of p-bumps formed on p-electrode layers, the occurrence of a faulty junction after mounting can be suppressed by placement of the n-bump at center of the bump array, because the position at the center is most resistant to occurrence of stress after the mounting. Employment of such a configuration of bump array increases reliability of mounting thereof while improving uniformity of light emission intensity in the semiconductor light emitting device having an increased size.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: March 6, 2012
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Shinji Ishitani
  • Patent number: 8077447
    Abstract: An electronic element package includes a plate-like sensor substrate with a detector formed thereon, and a plate-like first cover substrate and a plate-like second cover substrate joined directly or indirectly to a top surface and a bottom surface, respectively, of the sensor substrate so that the sensor substrate is located between the first and second cover substrates, the sensor substrate including, a frame surrounding the detector via a space, beams joining the detector to the frame, and an electrode disposed on the frame and electrically connected to the detector, one of the first cover substrate and the second cover substrate having a through-hole which contacts an electrode. The electronic element package enables a reduction in thickness and offers improved reliability.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: December 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Shinji Ishitani
  • Patent number: 7994634
    Abstract: A semiconductor element is provided that includes a semiconductor substrate, a circuit element disposed on the substrate, and a through-hole formed in the substrate having a stripe-like concavo-convex structure on its sidewall with stripes formed in the direction of the thickness of the semiconductor substrate.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: August 9, 2011
    Assignee: Panasonic Corporation
    Inventors: Takeshi Kita, Kazushi Higashi
  • Patent number: 7955974
    Abstract: When forming a resin material in a through hole, an electrode pad is formed in the bottom portion of the through hole, an insulating material is formed about the periphery of the through hole and a conductive material is formed in the central portion by an inkjet method, inkjet-ejected resins being ejected in such a manner that concavo-convex indentations and projections are formed in the surface thereof, whereby the adhesiveness between the insulating material and the conductive material and the adhesiveness between the insulating material and the inner walls of the through hole can be improved. Therefore, it is possible to suppress mechanical defects such as detachment of conductive material at the interfaces between the inner surface of the through hole and the resin or conductor layer, or electrical defects such as insulation defects, conduction defects, or the like.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: June 7, 2011
    Assignee: Panasonic Corporation
    Inventor: Kazushi Higashi
  • Publication number: 20110057326
    Abstract: An electrode on a first surface of a semiconductor substrate and a second surface of the semiconductor substrate are connected with each other by a through electrode. A through hole is formed through the semiconductor substrate from the second surface of the semiconductor substrate to an interlayer insulating film on the first surface, and an insulating film is formed on a side surface and a bottom surface of the through hole as well as on the second surface of the semiconductor substrate, so that by simultaneously etching the insulating film on the bottom surface of the through hole and the interlayer insulating film, thus formed, the through hole is formed so as to reach the electrode on the first surface of the semiconductor substrate.
    Type: Application
    Filed: December 1, 2009
    Publication date: March 10, 2011
    Inventors: Takayuki Kai, Kazushi Higashi, Takeshi Kita, Hitoshi Yamanishi, Takafumi Okuma
  • Patent number: 7790594
    Abstract: It is an object of the invention to provide an electronic part capable of forming an accurate gap between opposing substrates while also capable of decreasing the area of the electronic part, and a method of producing the same. A second electrode portion (6), having a core pattern (7) and a bump pattern (8) covering the surface thereof, is provided on a device substrate (1), the core pattern (7) is made of a material having hardness greater than that of the bump pattern (8), a first electrode portion (5) of the same material as the bump pattern (8) is provided on a bonding substrate (2), and a functional portion of the device substrate (1) and the first electrode portion (5) are electrically connected by direct bonding of the first electrode portion (5) and the bump pattern (8).
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: September 7, 2010
    Assignee: Panasonic Corporation
    Inventor: Kazushi Higashi
  • Patent number: 7692292
    Abstract: A first container member (9, 109, 212) mounting an electronic device (71, 171, 261) thereon and a second container member (2, 102, 202) are bonded with an adhesive (3, 103) or a metal layer (103, 251). Thus an inner space (90, 190, 211) is formed and the electronic device can be closed in the inner space at a low temperature. In the case the adhesive is used, an exposed surface of the adhesive is coated with a metal film (4) to improve the closeness of the inner space. Further, an electronic device (261, 272) may be mounted on the second container member so as to increase the electronic device arrangement density in a packaged electronic device.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: April 6, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Shinji Ishitani
  • Publication number: 20100012965
    Abstract: In a semiconductor light emitting device having a matrix of a plurality of bumps composed of one n-bump formed on an n-electrode layer and of a large number of p-bumps formed on p-electrode layers, occurrence of faulty junction in the n-bump fewer than the p-bumps after mounting can be suppressed by placement of the n-bump at center of the bump array that is most resistant to occurrence of stress after the mounting. Employment of such a configuration of bump array increases reliability of mounting thereof while improving uniformity of light emission intensity in the semiconductor light emitting device having an increased size.
    Type: Application
    Filed: July 12, 2006
    Publication date: January 21, 2010
    Inventors: Kazushi Higashi, Shinji Ishitani
  • Patent number: 7646095
    Abstract: In a semiconductor device of the present invention, in order that the contact of electrodes formed on a film substrate with edge parts of a semiconductor element at the time such as when the semiconductor element is mounted thereon may be reliably prevented, in the semiconductor element mounted on at least one surface of the film substrate having the electrodes, an insulating protection part is formed at a desired position of the surface opposed to the electrodes, and the distance between the semiconductor element and the film substrate is set at not less than 10 ?m.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: January 12, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Kouichi Yoshida, Shinji Ishitani, Daido Komyoji
  • Publication number: 20090280647
    Abstract: When forming a resin material in a through hole, an electrode pad is formed in the bottom portion of the through hole, an insulating material is formed about the periphery of the through hole and a conductive material is formed in the central portion by an inkjet method, inkjet-ejected resins being ejected in such a manner that concavo-convex indentations and projections are formed in the surface thereof, whereby the adhesiveness between the insulating material and the conductive material and the adhesiveness between the insulating material and the inner walls of the through hole can be improved. Therefore, it is possible to suppress mechanical defects such as detachment of conductive material at the interfaces between the inner surface of the through hole and the resin or conductor layer, or electrical defects such as insulation defects, conduction defects, or the like.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 12, 2009
    Applicant: Panasonic Corporation
    Inventor: Kazushi HIGASHI
  • Patent number: 7615406
    Abstract: By joining a lid member to a base member, internal electrodes put in contact with the lid member and an electronic device connected to the internal electrodes are placed in an internal space located in between the base member and the lid member. By performing etching from a surface of the lid member on a side opposite from the base member by a prescribed method, through holes that reach the surface of the internal electrodes are formed. A conductive material is applied to the through holes, and external electrodes connected to the internal electrodes are formed in a plane, completing a thin type electronic device package.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: November 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Yukihiro Maegawa
  • Publication number: 20090243120
    Abstract: A semiconductor element is provided that includes a semiconductor substrate, a circuit element disposed on the substrate, and a through-hole formed in the substrate having a stripe-like concavo-convex structure on its sidewall with stripes formed in the direction of the thickness of the semiconductor substrate.
    Type: Application
    Filed: March 23, 2009
    Publication date: October 1, 2009
    Applicant: Panasonic Corporation
    Inventors: Takeshi KITA, Kazushi HIGASHI
  • Patent number: 7554126
    Abstract: An LED chip of the present invention has a structure in which an n-type semiconductor layer and a p-type semiconductor layer are successively formed on the lower face of an element substrate, with the p-type semiconductor layer being formed on an area except for an area for an n-electrode. A first n-electrode is formed on the area for the n-electrode and a first p-electrode is formed on the p-type semiconductor layer. A first insulating layer having openings and is formed on the first n-electrode and the first p-electrode, and a second n-electrode and a second p-electrode having virtually the same size are formed on the first insulating layer. With this arrangement, the electrode on the n-type semiconductor layer can be made larger, thereby a mounting process of LED chips onto a circuit board can be executed by using solder at low costs.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: June 30, 2009
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Shinji Ishitani
  • Patent number: 7549567
    Abstract: Component 3 is pressed onto a circuit board 4 so that their respective metal interconnects 5, 6 are in close contact with each other, and ultrasonic vibration is applied to the suction nozzle 14 holding the component 3. Friction is thereby generated between metal interconnects 5, 6 whereby the component 3 is bonded on circuit substrate. Suction nozzle 14 for handling components is made of stainless steel and has a working face 14a provided with a hardened layer 14b, or alternatively, suction nozzle 14 may have a suction head 14c having a working face 14a made of cemented carbide. Working face 14a of suction nozzle 14 is refined by polishing as required during the mounting operation.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: June 23, 2009
    Assignee: Panasonic Corporation
    Inventors: Kazushi Higashi, Shozo Minamitani, Shinji Kanayama, Kenji Takahashi
  • Publication number: 20090140410
    Abstract: It is an object of the invention to provide an electronic part capable of forming an accurate gap between opposing substrates while also capable of decreasing the area of the electronic part, and a method of producing the same. A second electrode portion (6), having a core pattern (7) and a bump pattern (8) covering the surface thereof, is provided on a device substrate (1), the core pattern (7) is made of a material having hardness greater than that of the bump pattern (8), a first electrode portion (5) of the same material as the bump pattern (8) is provided on a bonding substrate (2), and a functional portion of the device substrate (1) and the first electrode portion (5) are electrically connected by direct bonding of the first electrode portion (5) and the bump pattern (8).
    Type: Application
    Filed: November 20, 2008
    Publication date: June 4, 2009
    Applicant: Panasonic Corporation
    Inventor: Kazushi Higashi
  • Publication number: 20080277771
    Abstract: By joining a lid member to a base member, internal electrodes put in contact with the lid member and an electronic device connected to the internal electrodes are placed in an internal space located in between the base member and the lid member. Then, by performing etching from a surface of the lid member on the side opposite from the base member by a prescribed method, through holes that reach the surface of the internal electrodes are formed. A conductive material is given to the through holes, and external electrodes connected to the internal electrodes are formed in a plane, completing a thin type electronic device package.
    Type: Application
    Filed: January 26, 2006
    Publication date: November 13, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kazushi Higashi, Yukihiro Maegawa
  • Publication number: 20080137270
    Abstract: An electronic element package includes a plate-like sensor substrate with a detector formed thereon, and a plate-like first cover substrate and a plate-like second cover substrate joined directly or indirectly to a top surface and a bottom surface, respectively, of the sensor substrate so that the sensor substrate is located between the first and second cover substrates, the sensor substrate including, a frame surrounding the detector via a space, beams joining the detector to the frame, and an electrode disposed on the frame and electrically connected to the detector, one of the first cover substrate and the second cover substrate having a through-hole which contacts an electrode. The electronic element package enables a reduction in thickness and offers improved reliability.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 12, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazushi Higashi, Shinji Ishitani
  • Patent number: 7350684
    Abstract: A preheat device (160) is provided to execute, before forming bumps (16) to electrode parts (15), a pre-formation temperature control for bonding promotion to promote bonding between the electrode parts and the bumps during bump formation. Metal particles of the electrode parts can be changed to an appropriate state before the bump formation. Phenomenally, a bonding state between the electrode parts and the bumps can be improved as compared with the conventional art. In a further arrangement of the present invention, semiconductor components with bumps can be heated under a bonding strength improvement condition by a bonding stage (316) through controlling the heating by a controller (317).
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: April 1, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shoriki Narita, Koichi Yoshida, Masahiko Ikeya, Takaharu Mae, Shinji Kanayama, Makoto Imanishi, Kazushi Higashi, Kenji Fukumoto, Hiroshi Wada
  • Publication number: 20070262338
    Abstract: An LED chip of the present invention has a structure in which an n-type semiconductor layer and a p-type semiconductor layer are successively formed on the lower face of an element substrate, with the p-type semiconductor layer being formed on an area except for an area for an n-electrode. A first n-electrode is formed on the area for the n-electrode and a first p-electrode is formed on the p-type semiconductor layer. A first insulating layer having openings and is formed on the first n-electrode and the first p-electrode, and a second n-electrode and a second p-electrode having virtually the same size are formed on the first insulating layer. With this arrangement, the electrode on the n-type semiconductor layer can be made larger, thereby a mounting process of LED chips onto a circuit board can be executed by using solder at low costs.
    Type: Application
    Filed: September 22, 2005
    Publication date: November 15, 2007
    Inventors: Kazushi Higashi, Shinji Ishitani