Patents by Inventor Kazushi Kawaguchi

Kazushi Kawaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160028161
    Abstract: An antenna apparatus includes a dielectric substrate, a ground plate, a patch antenna provided with a patch radiating element, and a plurality of EBGs (Electromagnetic Band Gaps). The EBGs are composed of patch-shaped patterns formed on a surface of the substrate and connecting conductors electrically connecting the patch-shaped patterns and the ground plate. Each EBG is arranged to provide an EBG absent region having no EBG on the surface of the substrate. The patch radiating element is arranged within the EBG absent region. The EBG absent region is formed such that distances (absent distances) in a dominant polarized wave direction changes into a plurality of types depending on the position on a vertical patch line, where the distances range, to the boundary of the region, from an arbitrary position on the virtual patch line which is perpendicular to the dominant polarized wave direction of the patch antenna.
    Type: Application
    Filed: March 12, 2014
    Publication date: January 28, 2016
    Inventors: Kazushi Kawaguchi, Yuji Sugimoto, Asahi Kondo, Masanobu Yukumatsu
  • Publication number: 20160013557
    Abstract: An antenna device 1 has a dielectric substrate 2, a patch antenna 5 and electric power absorbing passive elements 21, 24 formed on a surface of the dielectric substrate. Each electric power absorbing passive element 21, 24 is formed between the patch antenna 5 and an edge portion in a polarized wave direction of the dielectric substrate 2. The electric power absorbing passive elements 21, 24 absorb a part of electric power received by the patch antenna 5. This makes it possible to suppress a surface current flowing to the edge portions of the dielectric substrate on a conductive plate (a front-surface conductor plate 3 or a back surface conductor plate 4) on the dielectric substrate.
    Type: Application
    Filed: December 11, 2013
    Publication date: January 14, 2016
    Inventors: Kazushi Kawaguchi, Yuji Sugimoto, Masanobu Yukumatsu, Asahi Kondo
  • Patent number: 5453902
    Abstract: A headlamp for motor vehicles in which an inner lens formed with distribution beam control steps can easily be fastened to the front opening of the reflector. Holes, which receive respective protrusions protruding from the lower edge of the inner lens, are formed in the lower surface of the reflector, and cutout portions provided on the front end of the upper surface of the reflector are located further rearward than the protrusions, whereby the inner lens maintains engagement with the front opening of the reflector lens contact faces by its own weight. The upper edge of the inner lens can easily be fastened to the front end of the upper surface.
    Type: Grant
    Filed: March 22, 1994
    Date of Patent: September 26, 1995
    Assignee: Koito Manufacturing Co., Ltd.
    Inventors: Shinji Watanabe, Kazushi Kawaguchi
  • Patent number: 5451540
    Abstract: The present invention relates to a method for forming an oxide film on a semiconductor substrate by a buffer LOCOS method, has for its object to prevent anomalous formation of the oxide film and also to suppress a spread of a bird's beak from an oxide film forming region, and includes a process of forming a polycrystalline or amorphous silicon film 23 on a semiconductor substrate 21, a process of exposing the silicon film 23 to a fluoric acid medium, a process of forming an oxidation-resistant film 24 on the silicon film 23, a process of patterning the oxidation-resistant film 24, land oxidizing the silicon film 23 and the semiconductor substrate 21 selectively with the oxidation-resistant film 24 as a mask.
    Type: Grant
    Filed: October 20, 1994
    Date of Patent: September 19, 1995
    Assignee: Fujitsu Limited
    Inventors: Kazushi Kawaguchi, Koichi Hashimoto
  • Patent number: 4824794
    Abstract: A bipolar transistor having self-aligned base and emitter regions is fabricated in a silicon layer which is epitaxially grown on a substrate so as to fill up a cavity formed through a polysilicon layer deposited on the substrate. The polysilicon layer is doped with impurities for creating an extrinsic base region in the epitaxially grown silicon layer and is insulated from the emitter electrode by a dielectric layer formed thereon. The dielectric layer can be provided by selectively oxidizing the polysilicon layer. Thus, the step formed at the emitter electrode is small and equal to the thickness of the dielectric layer, about 3000 .ANG., for example, thereby eliminating the faulty step coverage in the prior art self-aligned bipolar transistor usually having the step as large as 1 micron.
    Type: Grant
    Filed: March 14, 1988
    Date of Patent: April 25, 1989
    Assignee: Fujitsu Limited
    Inventors: Akira Tabata, Motoshu Miyajima, Kazushi Kawaguchi