Patents by Inventor Kazushi Nakano
Kazushi Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8285400Abstract: There is provided a digital controller which can reduce a variation in output voltage as compared to the conventional digital controller at the time of abrupt changes in load and in input of a power amplifier. The digital controller is built in the power amplifier for supplying an output voltage vo to a load and is equipped with a manipulated variable calculating unit which detects the output voltage vo to calculate a manipulated variable ?1 and a signal generating unit which converts the manipulated variable ?1 into a signal for making the power amplifier operate. A feedforward function from an equivalent disturbance qy caused by the variation in the load is replaced by a feedback function from the output voltage vo and the manipulated variable ?1, thereby allowing a transfer characteristic from the disturbance qy to the output voltage vo to result in a quadratic differential characteristic.Type: GrantFiled: December 11, 2007Date of Patent: October 9, 2012Assignee: TDK-Lambda CorporationInventors: Kouji Higuchi, Kazushi Nakano, Tatsuyoshi Kajikawa, Eiji Takegami, Kazushi Watanabe, Satoshi Tomioka
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Patent number: 8099199Abstract: There is provided a digital controller which can generate no oscillation even if sensing a load side and enables control of supplying a desired voltage to the load. In an power amplifier which supplies an output voltage vo to the load connected via a load connecting line, a load voltage vL and the output voltage vo are periodically sampled to calculate a manipulating variable ?1 from the output voltage vo, the load voltage vL and an arbitrary target value r. Based on the manipulating variable ?1 calculated, a control signal is output to the power amplifier. As a result, when connecting an LC filter with a load device 9 of the power amplifier intended for a control target and besides the load connecting line is long, a robust digital controller without generating oscillation even if sensing the load side is performed can be realized.Type: GrantFiled: March 22, 2007Date of Patent: January 17, 2012Assignee: TDK-Lameda CorporationInventors: Eiji Takegami, Kazushi Watanabe, Satoshi Tomioka, Kouji Higuchi, Kazushi Nakano, Tatsuyoshi Kajikawa
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Publication number: 20100114399Abstract: There is provided a digital controller which can reduce a variation in output voltage as compared to the conventional digital controller at the time of abrupt changes in load and in input of a power amplifier. The digital controller is built in the power amplifier for supplying an output voltage vo to a load and is equipped with a manipulated variable calculating unit which detects the output voltage vo to calculate a manipulated variable ?1 and a signal generating unit which converts the manipulated variable ?1 into a signal for making the power amplifier operate. A feedforward function from an equivalent disturbance qy caused by the variation in the load is replaced by a feedback function from the output voltage vo and the manipulated variable ?1, thereby allowing a transfer characteristic from the disturbance qy to the output voltage vo to result in a quadratic differential characteristic.Type: ApplicationFiled: December 11, 2007Publication date: May 6, 2010Applicants: UNIVERSITY OF ELECTRO-COMMUNICATIONS, TDK-LAMBDA CORPORATION, KABUSHIKI KAISHA CAMPUSCREATEInventors: Kouji Higuchi, Kazushi Nakano, Tatsuyoshi Kajikawa, Eiji Takegami, Kazushi Watanabe, Satoshi Tomioka
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Patent number: 7620462Abstract: A robust digital controller is equipped with a high degree of approximation and is able to incorporate a novel two-degree-of-freedom robust digital control system without substantially considering the magnitude of the control inputs and there is provided its designing device. A control compensating means is configured as an integral type control system in which a discrete transfer function Wry (z) between a target value r and a controlled variable y is approximated to a higher-approximate quadratic approximate model transfer function Wm (z) and an arithmetic processing can be performed within the digital controller based on the model transfer function Wm (z). Further, the designing device automatically calculates parameters constituting the control system. Consequently, a robust digital controller can be easily realized that is equipped with a high degree of approximation as compared with a conventional approximate digital control system for realizing a first-order model and is robust against output noises.Type: GrantFiled: July 28, 2005Date of Patent: November 17, 2009Assignees: University of Electro-Communications, Kabushiki Kaisha Campuscreate, TDK-Lambda CorporationInventors: Kouji Higuchi, Kazushi Nakano, Tatsuyoshi Kajikawa, Eiji Takegami, Kazushi Watanabe, Satoshi Tomioka
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Patent number: 7538014Abstract: Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse laser beam (energy beam) emitted from an XeCl excimer laser by 150 times so as to heat the amorphous film at such a temperature as to partially melt crystal grains having the {100} orientations with respect to the vertical direction of a substrate and melt amorphous film or crystal grains having face orientations other than the {100} orientations. Silicon crystals having the {100} orientations newly occur between a silicon oxide film and liquid-phase silicon and are bonded to each other at random, to newly form crystal grains having the {100} orientations.Type: GrantFiled: October 26, 2006Date of Patent: May 26, 2009Assignee: Sony CorporationInventors: Dharam Pal Gosain, Akio Machida, Kazushi Nakano, Toshio Fujino, Junichi Sato
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Publication number: 20090099704Abstract: There is provided a digital controller which can generate no oscillation even if sensing a load side and enables control of supplying a desired voltage to the load. In an power amplifier which supplies an output voltage vo to the load connected via a load connecting line, a load voltage vL and the output voltage vo are periodically sampled to calculate a manipulating variable ?1 from the output voltage vo, the load voltage vL and an arbitrary target value r. Based on the manipulating variable ?1 calculated, a control signal is output to the power amplifier. As a result, when connecting an LC filter with a load device 9 of the power amplifier intended for a control target and besides the load connecting line is long, a robust digital controller without generating oscillation even if sensing the load side is performed can be realized.Type: ApplicationFiled: March 22, 2007Publication date: April 16, 2009Applicants: UNIVERSITY OF ELECTRO- COMMUNICATIONS, DENSEI-LAMBDA KABUSHIKI KAISHA, KABUSHIKI KAISHA CAMPUSCREATEInventors: Eiji Takegami, Kazushi Watanabe, Satoshi Tomioka, Kouji Higuchi, Kazushi Nakano, Tatsuyoshi Kajikawa
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Publication number: 20070250186Abstract: A robust digital controller is equipped with a high degree of approximation and is able to incorporate a novel two-degree-of-freedom robust digital control system without substantially considering the magnitude of the control inputs and there is provided its designing device. A control compensating means is configured as an integral type control system in which a discrete transfer function Wry(z) between a target value r and a controlled variable y is approximated to a higher-approximate quadratic approximate model transfer function Wm(z) and an arithmetic processing can be performed within the digital controller based on the model transfer function Wm(z). Further, the designing device automatically calculates parameters constituting the control system. Consequently, a robust digital controller can be easily realized that is equipped with a high degree of approximation as compared with a conventional approximate digital control system for realizing a first-order model and is robust against output noises.Type: ApplicationFiled: July 28, 2005Publication date: October 25, 2007Applicant: UNIVERSITY OF ELECTRO-COMMUNICATIONSInventors: Kouji Higuchi, Kazushi Nakano, Tatsuyoshi Kajikawa, Eiji Takegami, Kazushi Watanabe, Satoshi Tomioka
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Patent number: 7189665Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.Type: GrantFiled: December 2, 2005Date of Patent: March 13, 2007Assignee: Sony CorporationInventors: Kazushi Nakano, Yukihisa Hitsuda, Toshio Fujino, Michinori Shiomi, Junichi Sato
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Publication number: 20070051302Abstract: Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse laser beam (energy beam) emitted from an XeCl excimer laser by 150 times so as to heat the amorphous film at such a temperature as to partially melt crystal grains having the {100} orientations with respect to the vertical direction of a substrate and melt amorphous film or crystal grains having face orientations other than the {100} orientations. Silicon crystals having the {100} orientations newly occur between a silicon oxide film and liquid-phase silicon and are bonded to each other at random, to newly form crystal grains having the {100} orientations.Type: ApplicationFiled: October 26, 2006Publication date: March 8, 2007Inventors: Dharam Gosain, Akio Machida, Kazushi Nakano, Toshio Fujino, Junichi Sato
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Patent number: 7169690Abstract: Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse laser beam (energy beam) emitted from an XeCl excimer laser by 150 times so as to heat the amorphous film at such a temperature as to partially melt crystal grains having the {100} orientations with respect to the vertical direction of a substrate and melt amorphous film or crystal grains having face orientations other than the {100} orientations. Silicon crystals having the {100} orientations newly occur between a silicon oxide film and liquid-phase silicon and are bonded to each other at random, to newly form crystal grains having the {100} orientations.Type: GrantFiled: April 5, 2005Date of Patent: January 30, 2007Assignee: Sony CorporationInventors: Dharam Pal Gosain, Akio Machida, Kazushi Nakano, Toshio Fujino, Junichi Sato
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Patent number: 7144793Abstract: Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse laser beam (energy beam) emitted from an XeCl excimer laser by 150 times so as to heat the amorphous film at such a temperature as to partially melt crystal grains having the {100} orientations with respect to the vertical direction of a substrate and melt amorphous film or crystal grains having face orientations other than the {100} orientations. Silicon crystals having the {100} orientations newly occur between a silicon oxide film and liquid-phase silicon and are bonded to each other at random, to newly form crystal grains having the {100} orientations.Type: GrantFiled: August 21, 2003Date of Patent: December 5, 2006Assignee: Sony CorporationInventors: Dharam Pal Gosain, Akio Machida, Kazushi Nakano, Toshio Fujino, Junichi Sato
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Publication number: 20060084246Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.Type: ApplicationFiled: December 2, 2005Publication date: April 20, 2006Inventors: Kazushi Nakano, Yukihisa Hitsuda, Toshio Fujino, Michinori Shiomi, Junichi Sato
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Patent number: 6972246Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.Type: GrantFiled: May 28, 2004Date of Patent: December 6, 2005Assignee: Sony CorporationInventors: Kazushi Nakano, Yukihisa Hitsuda, Toshio Fujino, Michinori Shiomi, Junichi Sato
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Publication number: 20050172888Abstract: Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse laser beam (energy beam) emitted from an XeCl excimer laser by 150 times so as to heat the amorphous film at such a temperature as to partially melt crystal grains having the {100} orientations with respect to the vertical direction of a substrate and melt amorphous film or crystal grains having face orientations other than the {100} orientations. Silicon crystals having the {100} orientations newly occur between a silicon oxide film and liquid-phase silicon and are bonded to each other at random, to newly form crystal grains having the {100} orientations.Type: ApplicationFiled: April 5, 2005Publication date: August 11, 2005Inventors: Dharam Gosain, Akio Machida, Kazushi Nakano, Toshio Fujino, Junichi Sato
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Publication number: 20050006646Abstract: A manufacturing method for a crystalline semiconductor material including a plurality of semiconductor crystal grains is provided. The manufacturing method includes forming an amorphous or polycrystalline semiconductor layer on a substrate having a flat surface; forming a plurality of projections each having a side wall surface substantially perpendicular to the flat surface of the substrate, a height set in the range of about 1 nm to less than or equal to about ¼ of the thickness of the semiconductor layer, and a lateral dimension set in the range of about 3 ?m to about 18 ?m in a direction parallel to the flat surface of the substrate; and heating the semiconductor layer a number of times by using a pulsed laser thereby forming the crystalline semiconductor material including the crystal grains each having a specific plane orientation with respect to a direction perpendicular to the flat surface of the substrate so that the crystal grains respectively correspond to the projections.Type: ApplicationFiled: May 28, 2004Publication date: January 13, 2005Inventors: Kazushi Nakano, Yukihisa Hitsuda, Toshio Fujino, Michinori Shiomi, Junichi Sato
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Publication number: 20040209447Abstract: Disclosed are a method of producing a crystalline semiconductor material capable of improving the crystallinity and a method of fabricating a semiconductor device using the crystalline semiconductor material. An amorphous film is uniformly irradiated with a pulse laser beam (energy beam) emitted from an XeCl excimer laser by 150 times so as to heat the amorphous film at such a temperature as to partially melt crystal grains having the {100} orientations with respect to the vertical direction of a substrate and melt amorphous film or crystal grains having face orientations other than the {100} orientations. Silicon crystals having the {100} orientations newly occur between a silicon oxide film and liquid-phase silicon and are bonded to each other at random, to newly form crystal grains having the {100} orientations.Type: ApplicationFiled: August 21, 2003Publication date: October 21, 2004Inventors: Dharam Pal Gosain, Akio Machida, Kazushi Nakano, Toshio Fujino, Junichi Sato
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Patent number: 6031244Abstract: A luminescent semiconductor device comprises: an active layer composed of a Group II-VI semiconductor device which comprises at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium, manganese and mercury, and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium. the Group II-VI compound semiconductor forming said active layer contains at least one element selected from the group consisting of magnesium, beryllium and cadmium as the Group II element and tellurium as the Group VI element. At least one antidiffusion layer preventing diffusion of these elements from the active layer is provided on at least one surface of the active layer.Type: GrantFiled: December 8, 1997Date of Patent: February 29, 2000Assignee: Sony CorporationInventors: Hiroyasu Noguchi, Kazushi Nakano, Akira Ishibashi, Atsushi Toda, Satoshi Taniguchi, Tomonori Hino, Eisaku Kato
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Patent number: 5898662Abstract: A semiconductor light emitting device comprises: a compound semiconductor substrate; an n-type cladding layer on the compound semiconductor substrate; an active layer on the n-type cladding layer; a p-type cladding layer on the active layer: and a p-type contact layer on the p-type cladding layer, the n-type cladding layer, the active layer, the p-type cladding layer and the p-type contact layer being made of II-VI compound semiconductors containing at least one of group II elements selected from the group consisting of Zn, Cd, Mg, Hg and Be and at least one of group VI elements selected from the group consisting of S, Se, Te and O, characterized in that at least the active layer has undulations and at least the p-type layer is flat.Type: GrantFiled: November 10, 1997Date of Patent: April 27, 1999Assignee: Sony CorporationInventors: Akira Ishibashi, Satoshi Taniguchi, Tomonori Hino, Takashi Kobayashi, Kazushi Nakano, Norikazu Nakayama
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Patent number: 5872023Abstract: The semiconductor light emitting device includes a semiconductor substrate (1), a first conductivity type first cladding layer (2) deposited on the semiconductor substrate (1), an active layer (4) deposited on the first cladding layer (2), and the second conductivity type second cladding layer (6) deposited on the active layer (4). The first and the second cladding layers (2, 6) are made of the II/VI-compound semiconductors including at least one kind of II group elements such as Zn, Hg, Cd, Mg and at least one kind of VI group elements such as S, Se, Te. The lattice mismatching .DELTA.a/a (%) between at least one of the first cladding layer (2) and the second cladding layer (6) and the substrate is set within the range of -0.9%.ltoreq..DELTA.a/a.ltoreq.0.5% (reference symbols a and a.sub.c represent the lattice constant of the semiconductor substrate and the lattice constant of at least either of the first and second cladding layers, and .DELTA.a is obtained from .DELTA.a=a.sub.c -a).Type: GrantFiled: March 31, 1997Date of Patent: February 16, 1999Assignee: Sony CorporationInventors: Masashi Shiraishi, Satoshi Ito, Kazushi Nakano, Akira Ishibashi, Masao Ikeda, Hiroyuki Okuyama, Katsuhiro Akimoto, Tomonori Hino, Masakazu Ukita
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Patent number: 5828086Abstract: A semiconductor light emitting device ccomprises a first cladding layer, an active layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer and the second cladding layer has a superlattice structure comprising II-VI compound semiconductor. Another semiconductor light emitting device comprises a first cladding layer, a first guide layer, an active layer, a second guide layer and a second cladding layer which are stacked on a semiconductor substrate. At least a part of the first cladding layer, the first guide layer, the second cladding layer and the second guide layer has a superlattice structure. Still anothr semiconductor light emitting device comprises a defect decomposing layer, a defect blocking layer, a first cladding layer, an active layer, a second cladding layer which are stacked on a semiconductor substrate. The defect decomposing layer and the defect blocking layer comprise a superlattice structure.Type: GrantFiled: March 24, 1997Date of Patent: October 27, 1998Assignee: Sony CorporationInventors: Akira Ishibashi, Satoshi Matsumoto, Masaharu Nagai, Satoshi Ito, Shigetaka Tomiya, Kazushi Nakano, Etsuo Morita