Patents by Inventor Kazushi Nakazawa

Kazushi Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160322967
    Abstract: This circuit constant variable circuit changes the circuit constant of a passive element for which the impedance fluctuates according to the frequency of an AC current. The circuit constant variable circuit is equipped with a first bidirectional switch (Q1) connected in series, a series circuit (20) including a passive element (C1), and a second bidirectional switch (Q2) connected in parallel to the series circuit (20).
    Type: Application
    Filed: December 23, 2014
    Publication date: November 3, 2016
    Inventors: Satoru INAKAGATA, Hideki TAMURA, Yutaka IWAHORI, Kazushi NAKAZAWA, Mariko KIFUJI
  • Patent number: 8716756
    Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: May 6, 2014
    Assignee: Panasonic Corporation
    Inventors: Kazushi Nakazawa, Akiyoshi Tamura
  • Patent number: 8710548
    Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: April 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tsuyoshi Tanaka
  • Patent number: 8569843
    Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: October 29, 2013
    Assignee: Panasonic Corporation
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
  • Patent number: 8436399
    Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: May 7, 2013
    Assignee: Panasonic Corporation
    Inventors: Kazushi Nakazawa, Akiyoshi Tamura
  • Patent number: 8344463
    Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
  • Publication number: 20120012893
    Abstract: To provide a semiconductor transistor without variation in threshold voltage of an FET and a method of manufacturing the semiconductor transistor, the semiconductor transistor includes: a substrate; a first compound semiconductor layer formed above the substrate; a second compound semiconductor layer formed on the first compound semiconductor layer and having a bandgap larger than a bandgap of the first compound semiconductor layer; an oxygen-doped region formed by doping at least part of the second compound semiconductor layer with oxygen; a third compound semiconductor layer formed on the second compound semiconductor layer; a source electrode electrically connected to the first compound semiconductor layer; a drain electrode electrically connected to the first compound semiconductor layer; and a gate electrode formed on and in contact with the oxygen-doped region.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 19, 2012
    Applicant: PANASONIC CORPORATION
    Inventor: Kazushi NAKAZAWA
  • Publication number: 20110037101
    Abstract: A semiconductor device includes an undoped GaN layer (13), an undoped AlGaN layer (14), and a p-type GaN layer (15). In the p-type GaN layer (15), highly resistive regions (15a) are selectively formed. Resistance of the highly resistive regions (15a) can be increased by introducing a transition metal, for example, titanium.
    Type: Application
    Filed: March 27, 2009
    Publication date: February 17, 2011
    Inventors: Kazushi Nakazawa, Toshiyuki Takizawa, Tetsuzo Ueda, Daisuke Ueda
  • Publication number: 20110024797
    Abstract: In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.
    Type: Application
    Filed: October 13, 2010
    Publication date: February 3, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Kazushi NAKAZAWA, Satoshi NAKAZAWA, Tetsuzo UEDA, Tsuyoshi TANAKA, Masahiro HIKITA
  • Patent number: 7838904
    Abstract: In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: November 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Kazushi Nakazawa, Satoshi Nakazawa, Tetsuzo Ueda, Tsuyoshi Tanaka, Masahiro Hikita
  • Patent number: 7821030
    Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: October 26, 2010
    Assignee: Panasonic Corporation
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tsuyoshi Tanaka
  • Publication number: 20100244045
    Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.
    Type: Application
    Filed: June 7, 2010
    Publication date: September 30, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Manabu YANAGIHARA, Kazushi Nakazawa, Tsuyoshi Tanaka
  • Publication number: 20100224908
    Abstract: A semiconductor device according to the present invention includes a substrate; a nitride semiconductor layer formed above the substrate and having a laminated structure including at least three layers; a heterojunction bipolar transistor formed in a region of the nitride semiconductor layer; and a field-effect transistor formed in a region of the nitride semiconductor layer, the region being different from the region in which the heterojunction bipolar transistor is formed.
    Type: Application
    Filed: February 22, 2010
    Publication date: September 9, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Kazushi NAKAZAWA, Akiyoshi TAMURA
  • Publication number: 20100213503
    Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.
    Type: Application
    Filed: July 10, 2009
    Publication date: August 26, 2010
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tatsuo Morita, Yasuhiro Uemoto
  • Patent number: 7605441
    Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: October 20, 2009
    Assignee: Panasonic Corporation
    Inventors: Kazushi Nakazawa, Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Patent number: 7550821
    Abstract: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced apart from each other on an active region in the nitride semiconductor layer. An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface. A first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: June 23, 2009
    Assignee: Panasonic Corporation
    Inventors: Daisuke Shibata, Kazushi Nakazawa, Masahiro Hikita, Yasuhiro Uemoto, Tetsuzo Ueda, Manabu Yanagihara, Tsuyoshi Tanaka
  • Publication number: 20080179694
    Abstract: In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.
    Type: Application
    Filed: January 31, 2008
    Publication date: July 31, 2008
    Inventors: Kazushi NAKAZAWA, Satoshi NAKAZAWA, Tetsuzo UEDA, Tsuyoshi TANAKA, Masahiro HIKITA
  • Publication number: 20080149940
    Abstract: A nitride semiconductor device includes: a substrate; a nitride semiconductor layer formed on a main surface of the substrate and having a channel region through which electrons drift in a direction parallel to the main surface; and a plurality of first electrodes and a plurality of second electrodes formed spaced apart from each other on an active region in the nitride semiconductor layer. An interlayer insulating film is formed on the nitride semiconductor layer. The interlayer insulating film has openings that respectively expose the first electrodes and has a planarized top surface. A first electrode pad is formed in a region over the active region in the interlayer insulating film and is electrically connected to the exposed first electrodes through the respective openings.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 26, 2008
    Inventors: Daisuke SHIBATA, Kazushi Nakazawa, Masahiro Hikita, Yasuhiro Uemoto, Tetsuzo Ueda, Manabu Yanagihara, Tsuyoshi Tanaka
  • Publication number: 20070235768
    Abstract: A semiconductor device includes: a semiconductor layer made of a group-III nitride semiconductor and having a first surface and a second surface opposed to the first surface; a Schottky electrode formed on the first surface of the semiconductor layer; and an ohmic electrode electrically connected to the second surface of the semiconductor layer. The semiconductor layer has, in at least the upper portion thereof, highly-resistive regions selectively formed to have a high resistance.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 11, 2007
    Inventors: Kazushi Nakazawa, Hiroaki Ueno, Manabu Yanagihara, Yasuhiro Uemoto, Tsuyoshi Tanaka
  • Publication number: 20060197175
    Abstract: A semiconductor device includes a first semiconductor layer which is formed above a substrate, a Schottky electrode and an ohmic electrode which are formed on the first semiconductor layer to be spaced from each other and a second semiconductor layer which is formed to cover the first semiconductor layer with the Schottky electrode and the ohmic electrode exposed. The second semiconductor layer has a larger band gap than that of the first semiconductor layer.
    Type: Application
    Filed: March 1, 2006
    Publication date: September 7, 2006
    Inventors: Manabu Yanagihara, Kazushi Nakazawa, Tsuyoshi Tanaka