Abstract: The semiconductor apparatus according to the present invention includes: a second-conductivity-type first diffusion region formed on the semiconductor layer; a first-conductivity-type second diffusion region formed in the first diffusion region; a second-conductivity-type first high concentration diffusion region and a first-conductivity-type second high concentration diffusion region formed in the second diffusion region; a second-conductivity-type third high concentration diffusion region, separated by a given distance from the second diffusion region, in the first diffusion region; and a gate electrode formed above and between the first high concentration diffusion region and third high concentration diffusion region, with a gate insulation film interposed therebetween, where the gate electrode is formed overlapping the first high concentration diffusion region, and the gate electrode is electrically connected with the first high concentration diffusion region and second high concentration diffusion region

Abstract: The semiconductor apparatus according to the present invention includes: a second-conductivity-type first diffusion region formed on the semiconductor layer; a first-conductivity-type second diffusion region formed in the first diffusion region; a second-conductivity-type first high concentration diffusion region and a first-conductivity-type second high concentration diffusion region formed in the second diffusion region; a second-conductivity-type third high concentration diffusion region, separated by a given distance from the second diffusion region, in the first diffusion region; and a gate electrode formed above and between the first high concentration diffusion region and third high concentration diffusion region, with a gate insulation film interposed therebetween, where the gate electrode is formed overlapping the first high concentration diffusion region, and the gate electrode is electrically connected with the first high concentration diffusion region and second high concentration diffusion region

Abstract: Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.

Abstract: Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.

Abstract: A manufacturing method for a semiconductor device, comprising the steps of: (a) forming a body portion of a DMOS by implanting impurity ions of a second conductive type into a predetermined region of a well of a first conductive type that has been formed in a main surface of a semiconductor substrate a plurality of times while changing an implantation amount or an implantation energy or both of them; (b) forming a gate dielectric film on the semiconductor substrate in a gate electrode formation region at least within the well, followed by a gate electrode on the gate dielectric film so as to cross an end of the body portion; (c) forming diffusion layers of the first conductive type on both sides of the gate electrode by implanting impurity ions of the first conductive type (provided that at least one of the diffusion layers is formed within the body portion); and (d) forming a contact layer of the second conductive type by implanting impurities of the second conductive type into the body portion with a impuri

Abstract: A transistor comprising a P-type high concentration impurity diffusion layer which can also serve as an emitter for a parasitic PNP transistor wherein a layer of crystal defect obtained by ion implantation of inert impurity atoms or a compound thereof is arranged in the P-type high concentration impurity diffusion layer thereby decreasing the current amplification rate of the parasitic transistor.

Abstract: A method for fabricating a semiconductor device including carrying out an ion implantation into a predetermined region of a single-crystal silicon substrate to form therein an amorphized ion-implanted layer according to any one of the methods: (A) implanting an ion of an atom serving as carrier into the predetermined region, followed by implanting an ion of an electrically inert atom or molecule into the region, (B) implanting an ion of an electrically inert atom or molecule in the region, followed by implanting an ion of an atom serving as carrier in the region, and (C) implanting an ion of a molecule in which an atom serving as carrier is bonded to an electrically inert atom; annealing the substrate in an inert atmosphere to crystallize the amorphized ion-implanted layer again; and further annealing the substrate in an oxidizing atmosphere to eliminate defects at the interface of the substrate and the ion implantation layer.