Patents by Inventor Kazushi Wada
Kazushi Wada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8729650Abstract: A solid-state imaging device includes a layer including an on-chip lens above a sensor section, and the layer including the on-chip lens is composed of an inorganic film which transmits ultraviolet light. The layer including the on-chip lens may further include a planarizing film located below the on-chip lens. A method of fabricating a solid-state imaging device includes the steps of forming a planarizing film composed of a first inorganic film, forming a second inorganic film on the planarizing film, forming a lens-shaped resist layer on the second inorganic film, and etching back the resist layer to form an on-chip lens composed of the second inorganic film. The first inorganic film constituting the planarizing film and the second inorganic film constituting the on-chip lens preferably transmit ultraviolet light.Type: GrantFiled: April 14, 2008Date of Patent: May 20, 2014Assignee: Sony CorporationInventors: Kouichi Harada, Yasuhiro Ueda, Nobuhiko Umezu, Kazushi Wada, Yoshinori Toumiya, Takeshi Matsuda
-
Patent number: 8462252Abstract: At a transfer electrode to which a normally low transfer pulse is applied, the time period in which the negative potential is applied is long, and an electric field is applied to a gate insulating film, such that the device's reliability decreases. To overcome this drawback, a negative side potential (VL?) of a normally low vertical transfer pulse (V?3, V?4) is set smaller in the absolute value than a negative side potential (VL) of a normally high vertical transfer pulse (V?1, V?2). Thereby, while the influence of increase in the dark current is being suppressed, the electric field being applied to the gate insulating film is reduced.Type: GrantFiled: August 9, 2006Date of Patent: June 11, 2013Assignee: Sony CorporationInventor: Kazushi Wada
-
Patent number: 8395699Abstract: A method for manufacturing a solid-state imaging device, in which a photoelectric conversion portion to receive light with a light-receiving surface and generate a signal charge is disposed in a substrate, includes the steps of forming a metal light-shield layer above the substrate and in a region other than a region corresponding to the light-receiving surface, forming a light-reflection layer above the metal light-shield layer, and forming a photoresist pattern layer from a negative type photoresist film formed above the light-reflection layer, by conducting an exposing treatment and a developing treatment, wherein in the forming of the light-reflection layer, the light-reflection layer includes a shape corresponding to a pattern shape of the photoresist pattern layer, and the light-reflection layer is formed in such a way as to reflect exposure light to the photoresist film in conduction of the exposing treatment in the forming of the photoresist pattern layer.Type: GrantFiled: February 2, 2010Date of Patent: March 12, 2013Assignee: Sony CorporationInventors: Kazushi Wada, Yoichi Otsuka
-
Patent number: 8253142Abstract: A solid-state imaging device includes a layer including an on-chip lens above a sensor section, and the layer including the on-chip lens is composed of an inorganic film which transmits ultraviolet light. The layer including the on-chip lens may further include a planarizing film located below the on-chip lens. A method of fabricating a solid-state imaging device includes the steps of forming a planarizing film composed of a first inorganic film, forming a second inorganic film on the planarizing film, forming a lens-shaped resist layer on the second inorganic film, and etching back the resist layer to form an on-chip lens composed of the second inorganic film. The first inorganic film constituting the planarizing film and the second inorganic film constituting the on-chip lens preferably transmit ultraviolet light.Type: GrantFiled: August 28, 2000Date of Patent: August 28, 2012Assignee: Sony CorporationInventors: Kouichi Harada, Yasuhiro Ueda, Nobuhiko Umezu, Kazushi Wada, Yoshinori Toumiya, Takeshi Matsuda
-
Patent number: 8217431Abstract: A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer register and a channel stop region. This P type region adjusts potential in the lower layer region of the vertical transfer register and the channel stop region. Accordingly, since the potential in the lower layer region of the vertical transfer register and the channel stop region at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.Type: GrantFiled: April 9, 2009Date of Patent: July 10, 2012Assignee: Sony CorporationInventors: Kazushi Wada, Kouichi Harada, Shuji Otsuka, Mitsuru Sato
-
Publication number: 20100201855Abstract: A method for manufacturing a solid-state imaging device, in which a photoelectric conversion portion to receive light with a light-receiving surface and generate a signal charge is disposed in a substrate, includes the steps of forming a metal light-shield layer above the substrate and in a region other than a region corresponding to the light-receiving surface, forming a light-reflection layer above the metal light-shield layer, and forming a photoresist pattern layer from a negative type photoresist film formed above the light-reflection layer, by conducting an exposing treatment and a developing treatment, wherein in the forming of the light-reflection layer, the light-reflection layer includes a shape corresponding to a pattern shape of the photoresist pattern layer, and the light-reflection layer is formed in such a way as to reflect exposure light to the photoresist film in conduction of the exposing treatment in the forming of the photoresist pattern layer.Type: ApplicationFiled: February 2, 2010Publication date: August 12, 2010Applicant: SONY CORPORATIONInventors: Kazushi Wada, Yoichi Otsuka
-
Publication number: 20090194794Abstract: Crosstalk between the adjacent pixels can be prevented by a structure in which an overflow barrier is provided at the deep portion of a substrate. A partial P type region 150 is provided at the predetermined position of a lower layer region of the vertical transfer register 124 and a channel stop region 126. This P type region 150 is used to adjust potential in the lower layer region of the vertical transfer register 124 and the channel stop region 126 so that the potential may become smaller than that of the lower layer region of the photosensor 122 in a range from the minimum potential position of the vertical transfer register 124 to the overflow barrier 128. Accordingly, since the potential in the lower layer region of the vertical transfer register 124 and the channel stop region 126 at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.Type: ApplicationFiled: April 9, 2009Publication date: August 6, 2009Inventors: Kazushi WADA, Kouichi Harada, Shuji Otsuka, Mitsuru Sato
-
Patent number: 7535038Abstract: A solid-state image pickup device for preventing crosstalk between adjacent pixels by providing an overflow barrier at the deep potion of a substrate. A partial P type region is provided at the predetermined position of a lower layer region of the vertical transfer register and a channel stop region. This P type region adjusts potential in the lower layer region of the vertical transfer register and the channel stop region. Accordingly, since the potential in the lower layer region of the vertical transfer register and the channel stop region at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.Type: GrantFiled: August 11, 2003Date of Patent: May 19, 2009Assignee: Sony CorporationInventors: Kazushi Wada, Kouichi Harada, Shuji Otsuka, Mitsuru Sato
-
Publication number: 20080315340Abstract: A solid-state imaging device includes a layer including an on-chip lens above a sensor section, and the layer including the on-chip lens is composed of an inorganic film which transmits ultraviolet light. The layer including the on-chip lens may further include a planarizing film located below the on-chip lens. A method of fabricating a solid-state imaging device includes the steps of forming a planarizing film composed of a first inorganic film, forming a second inorganic film on the planarizing film, forming a lens-shaped resist layer on the second inorganic film, and etching back the resist layer to form an on-chip lens composed of the second inorganic film. The first inorganic film constituting the planarizing film and the second inorganic film constituting the on-chip lens preferably transmit ultraviolet light.Type: ApplicationFiled: April 14, 2008Publication date: December 25, 2008Applicant: Sony CorporationInventors: Kouichi Harada, Yasuhiro Ueda, Nobuhiko Umezu, Kazushi Wada, Yoshinori Toumiya, Takeshi Matsuda
-
Publication number: 20070064138Abstract: At a transfer electrode to which a normally low transfer pulse is applied, the time period in which the negative potential is applied is long, and an electric field is applied to a gate insulating film, such that the device reliability can decrease. To overcome this drawback, a negative side potential (VL?) of a normally low vertical transfer pulse (V?3, V?4) is set smaller in the absolute value than a negative side potential (VL) of a normally high vertical transfer pulse (V?1, V?2). Thereby, while the influence of increase in the dark current is being suppressed, the electric field applying to the gate insulating film is reduced.Type: ApplicationFiled: August 9, 2006Publication date: March 22, 2007Applicant: Sony CorporationInventor: Kazushi Wada
-
Publication number: 20060163617Abstract: Crosstalk between the adjacent pixels can be prevented by a structure in which an overflow barrier is provided at the deep potion of a substrate. A partial P type region 150 is provided at the predetermined position of a lower layer region of the vertical transfer register 124 and a channel stop region 126. This P type region 150 is used to adjust potential in the lower layer region of the vertical transfer register 124 and the channel stop region 126 so that the potential may become smaller than that of the lower layer region of the photosensor 122 in a range from the minimum potential position of the vertical transfer register 124 to the overflow barrier 128. Accordingly, since the potential in the lower layer region of the vertical transfer register 124 and the channel stop region 126 at both sides of the lower layer region is low, electric charges photoelectrically-converted by the sensor region are blocked by this potential barrier and cannot be diffused easily.Type: ApplicationFiled: August 11, 2003Publication date: July 27, 2006Inventors: Kazushi Wada, Kouichi Harada, Shuji Otsuza, Mitsuru Sato
-
Publication number: 20060163619Abstract: A solid state image pickup device in which an image pickup region composed of a plurality of light-receiving pixel portions 1 and a transfer register 2 for transferring in one direction the signal charges accumulated in the light-receiving pixel portions 1 is formed on the face layer portion side of a semiconductor substrate and which prevents the mixing of signals between the adjacent signals even in the case where an overflow barrier is formed at a deep position for the purpose of enhancing the sensitivity per unit area, wherein barrier regions 15 each being an impurity region continuing in a direction orthogonal to the transfer direction of the transfer register 2 over the entire region of the image pickup region are each formed at a position corresponding to a position between the light-receiving pixel portions 1 adjacent to each other in the transfer direction, whereby a sufficient potential barrier is formed and the mixing of signals is thereby prevented.Type: ApplicationFiled: December 5, 2003Publication date: July 27, 2006Inventor: Kazushi Wada
-
Patent number: 6809355Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a wavelength of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage Vth, and hence to enhance the reliability of the transfer or reset of electric charges.Type: GrantFiled: March 30, 2001Date of Patent: October 26, 2004Assignee: Sony CorporationInventor: Kazushi Wada
-
Patent number: 6403994Abstract: A solid-state imaging device includes a second conductive type impurity region formed in a first conductive type semiconductor substrate in an area corresponding to a pixel area, a high-resistivity semiconductor layer of the first conductive type formed on the semiconductor substrate including the impurity region, and an ion-implanted region of the first conductive type formed in at least one of the semiconductor substrate and the high-resistivity semiconductor layer in a peripheral area other than the pixel area. A method of fabricating the solid-state imaging device is also disclosed.Type: GrantFiled: August 17, 2000Date of Patent: June 11, 2002Assignee: Sony CorporationInventor: Kazushi Wada
-
Publication number: 20010052636Abstract: A solid-state imaging device having a gate structure including an oxide film and a nitride film includes upper layer films (for example, a planarization film, an insulating film, and a protective film) allowing ultraviolet rays having a frequency of 400 nm or less to pass therethrough; and a metal made shield film or an organic film capable of absorbing the ultraviolet rays formed in such a manner as to cover a region of the gate structure (for example, an output gate and a reset gate), excluding a light receiving portion and a transfer portion, of the solid-state imaging device. With this configuration, it is possible to prevent the shift of a threshold voltage vth, and hence to enhance the reliability of the transfer or reset of electric charges.Type: ApplicationFiled: March 30, 2001Publication date: December 20, 2001Inventor: Kazushi Wada
-
Patent number: 5929470Abstract: A CCD solid state imaging device can reduce a smear component. This CCD solid state imaging device comprises a plurality of photosensor sections (10) arranged in a matrix fashion, a vertical transfer register (5) having a transfer electrode (16) disposed at every column of the photosensor sections, a shunt line layer (33) connected to the transfer electrode (16) on the vertical transfer register (5), and a photo-shield layer (38) formed so as to surround the photosensor section 10 through an interlayer insulating layer (37) which covers the shunt layer (33), in which the interlayer insulating layer (37) is formed under an overhang portion (38a) of the photo-shield layer (38) to the photosensor section (10).Type: GrantFiled: July 25, 1996Date of Patent: July 27, 1999Assignee: Sony CorporationInventors: Kouichi Harada, Junichi Furukawa, Kazushi Wada, Takaaki Sarai
-
Patent number: 5763292Abstract: A CCD solid state imaging device can reduce a smear component. This CCD solid state imaging device comprises a plurality of photosensor sections (10) arranged in a matrix fashion, a vertical transfer register (5) having a transfer electrode (16) disposed at every column of the photosensor sections, a shunt line layer (33) connected to the transfer electrode (16) on the vertical transfer register (5), and a photo-shield layer (38) formed so as to surround the photosensor section 10 through an interlayer insulating layer (37) which covers the shunt layer (33), in which the interlayer insulating layer (37) is formed under an overhang portion (38a) of the photo-shield layer (38) to the photosensor section (10).Type: GrantFiled: June 7, 1995Date of Patent: June 9, 1998Assignee: Sony CorporationInventors: Kouichi Harada, Junichi Furukawa, Kazushi Wada, Takaaki Sarai
-
Patent number: 5614741Abstract: A CCD solid state imaging device can reduce a smear component. This CCD solid state imaging device comprises a plurality of photosensor sections (10) arranged in a matrix fashion, a vertical transfer register (5) having a transfer electrode (16) disposed at every column of the photosensor sections, a shunt line layer (33) connected to the transfer electrode (16) on the vertical transfer register (5), and a photo-shield layer (38) formed so as to surround the photosensor section 10 through an interlayer insulating layer (37) which covers the shunt layer (33), in which the interlayer insulating layer (37) is not formed under an overhang portion (38a) of the photo-shield layer (38) to the photosensor section (10).Type: GrantFiled: May 17, 1994Date of Patent: March 25, 1997Assignee: Sony CorporationInventors: Kouichi Harada, Junichi Furukawa, Kazushi Wada, Takaaki Sarai
-
Patent number: 5371384Abstract: Light emitting devices are formed on a surface of a solid state imaging device and are used as illumination light sources. In a solid state imaging device for use in an electro-endoscope or the like, an illumination light source need not be provided independently of the solid state imaging device. Hence, the electro-endoscope can be miniaturized and simplified in structure.Type: GrantFiled: June 24, 1993Date of Patent: December 6, 1994Assignee: Sony CorporationInventor: Kazushi Wada
-
Patent number: 5220185Abstract: A CCD shift register has a final transfer electrode which is formed only by a first polysilicon layer, and an output gate electrode which is formed by a second polysilicon layer. Under the output gate electrode, there is formed a doped region which is formed by a doping step of self alignment, independently of a doped region under the transfer electrodes. Therefore, it is possible to choose the impurity concentration and to adjust the potential level under the output gate electrode freely.Type: GrantFiled: August 10, 1992Date of Patent: June 15, 1993Assignee: Sony CorporationInventor: Kazushi Wada