Patents by Inventor Kazushige Ayukawa
Kazushige Ayukawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8711650Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: June 26, 2012Date of Patent: April 29, 2014Assignee: Renesas Electronics CorporationInventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 8432716Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: GrantFiled: December 6, 2010Date of Patent: April 30, 2013Assignee: Renesas Electronics CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20120271987Abstract: A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.Type: ApplicationFiled: April 30, 2012Publication date: October 25, 2012Inventors: Seiji MIURA, Kazushige AYUKAWA
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Publication number: 20120262992Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 8255622Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: September 15, 2011Date of Patent: August 28, 2012Assignee: Renesas Electronics CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 8223578Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: June 11, 2009Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 8185690Abstract: A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.Type: GrantFiled: June 27, 2011Date of Patent: May 22, 2012Assignee: Renesas Electronics CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20120005421Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: September 15, 2011Publication date: January 5, 2012Inventors: SEIJI MIURA, KAZUSHIGE AYUKAWA
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Publication number: 20110258373Abstract: A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Inventors: Seiji MIURA, Kazushige Ayukawa
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Patent number: 8024512Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: November 18, 2009Date of Patent: September 20, 2011Assignee: Renesas Electronics CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 7991954Abstract: A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.Type: GrantFiled: October 14, 2009Date of Patent: August 2, 2011Assignee: Renesas Electronics CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20110078366Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: ApplicationFiled: December 6, 2010Publication date: March 31, 2011Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 7872895Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: GrantFiled: May 21, 2009Date of Patent: January 18, 2011Assignee: Renesas Electronics CorporationInventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20100064101Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: ApplicationFiled: November 18, 2009Publication date: March 11, 2010Inventors: SEIJI MIURA, Kazushige AYUKAWA
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Publication number: 20100030952Abstract: A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. A memory system including a non-volatile memory (CHIP1), DRAM (CHIP3), a control circuit (CHIP2) and an information processing device (CHIP4) is configured. Data in FLASH is transferred to SRAM or DRAM in advance to speed up. Data transfer between the non-volatile memory (FLASH) and DRAM (CHIP3) can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. As data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction, the performance and the function of a mobile device can be enhanced.Type: ApplicationFiled: October 14, 2009Publication date: February 4, 2010Inventors: Seiji MIURA, Kazushige Ayukawa
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Patent number: 7624238Abstract: A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.Type: GrantFiled: June 16, 2006Date of Patent: November 24, 2009Assignee: Hitachi Ltd.Inventors: Seiji Miura, Kazushige Ayukawa
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Patent number: 7613880Abstract: A memory system including large-capacity ROM and RAM in which high-speed reading and writing are enabled is provided. A memory system including a non-volatile memory (CHIP1), DRAM (CHIP3), a control circuit (CHIP2) and an information processing device (CHIP4) is configured. Data in FLASH is transferred to SRAM or DRAM in advance to speed up. Data transfer between the non-volatile memory (FLASH) and DRAM (CHIP3) can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.Type: GrantFiled: November 27, 2003Date of Patent: November 3, 2009Assignee: Renesas Technology Corp.Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20090268502Abstract: A semiconductor device including a large capacity non-volatile memory and at least one random access memory, said the access time of said device being matched to the access time of each random access memory. The semiconductor memory device is comprised of: a non-volatile memory FLASH having a first reading time; a random access memory DRAM having a second reading time which is more than 100 times shorter than the first reading time; a circuit that includes a control circuit connected to both the FLASH and the DRAM and enabled to control accesses to those FLASH and DRAM; and a plurality of I/O terminals connected to the circuit. As a result, FLASH data is transferred to the DRAM before the DRAM is accessed, thereby matching the access time between the FLASH and the DRAM. Data is written back from the DRAM to the FLASH as needed, thereby keeping data matched between the FLASH and the DRAM and storing the data.Type: ApplicationFiled: May 21, 2009Publication date: October 29, 2009Inventors: Seiji Miura, Kazushige Ayukawa
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Publication number: 20090245004Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: ApplicationFiled: June 11, 2009Publication date: October 1, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou
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Patent number: 7554872Abstract: In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.Type: GrantFiled: January 19, 2005Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Kazushige Ayukawa, Seiji Miura, Yoshikazu Saitou