Abstract: An electronic equipment housing includes: a housing including a housing space that houses an electronic equipment and a workbench; and a first support provided in the housing, wherein the workbench includes: a base detachably attached to the first support; a placing plate, liftably coupled to the base, configured to place the electronic equipment on a placing surface; and a lifting mechanism configured to move the placing plate with respect to the base.

Abstract: A parallel processing apparatus and method for processing data transferred between a plurality of processors each having a storage. Each of the plurality of processors corresponds a global virtual address in a global virtual memory space where a parallel processing between the plurality of processors is performed and a local virtual address in a local virtual memory space where an individual process in one of the processors is performed to an identical real address.

Abstract: A system information storage section stores access information showing attributes for accessing a storage peculiar to a processor and storages peculiar to other processors by relating the access information to data. The system information storage section stores space identifying information for identifying each of plural kinds of virtual spaces allocated according to applications of the storages. A plurality of address translation sections translate virtual addresses into real addresses, corresponding to the plural kinds of virtual spaces on the basis of the access information. A selection section selects any one of the plurality of address translation sections on the basis of the space identifying information. A transfer control section reads the data of the storage on the basis of the real address obtained by the selected address translation section and transfers the data to other processors together with the access information and the space identifying information.

Abstract: A parallel processing system that has a synchronous function of creating a synchronous signal in a processing element to be synchronized by shifting synchronously from a program process to the next program process and can execute such a synchronous operation in a pipeline processing mode. The parallel processing system includes a plurality of signal lines arranged between a mutual connecting unit and each of the processing elements for transmitting the status information regarding each of the processing elements from the mutual connecting unit to all of the processing elements, and the transmitting circuit sequentially transmitting contents stored in the status storage unit to the plurality of signal lines, with predetermined phase difference, and then transmitting them in parallel to each of the processing elements. This parallel processing system is applicable to a computing system in which a plurality of processing elements share one program to execute a parallel processing operation.

Abstract: A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.

Abstract: A data processing unit is adapted to exchange data with another data processing unit via a network. The data processing unit includes a main storage for storing programs and data, an instruction processor for issuing transfer requests by executing programs stored in the main storage, and a transfer processor for enqueuing the transfer requests from the instruction processor into a transfer request queue, and for carrying out a transfer process between the main storage and the network based on each transfer request which is obtained from the transfer request queue. The transfer processor includes a failure display for displaying a failure when the failure occurs during the transfer process of each transfer request, a reference to and an erasure of a content of the failure display are possible from the instruction processor. The transfer process of the transfer request enqueued in the transfer request queue is prohibited during a time in which the failure is displayed in the failure display.

Abstract: A synchronous processing system including a plurality of processors and a communications network. Each processor includes a synchronization combination storage element, status storage element, control element, judging element and shifting element. The synchronization combination storage element stores synchronization combination information showing a group of the processors being synchronized during the parallel execution of a program. The synchronous status storage element stores synchronous status information indicating that a synchronous waiting status is reached after the processor has finished its processing. A storage control element transmits the synchronous status information to all other processors. A judging element judges whether the group of processors are in synchronism based on the synchronization combination information and the transmitted status information.

Abstract: A transfer request queue control system for a parallel computer system includes a plurality of processing units each having a main storage storing instructions and data. An instruction processor reads the instructions from the main storage and executes the instructions. A transfer processor performs data transfers in packets, each comprising a header and body data and each data transfer comprising one or more packets. A network couples transmitting and receiving processing units, which are to perform a data transfer based on information included in the header of each packet, the header information being related to a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor performs parallel processing by making a data transfer between the main storage and the network in successive packets, depending on the attribute of the memory access.

Abstract: A parallel processing system including a plurality of processing units each having a main storage storing instructions and data, an instruction processor reading the instructions from the main storage and executing the instructions, and a transfer processor for making a data transfer in units of a packet which is made up of a header and body data. The parallel processing system further includes a network coupling two processing units which are to make the data transfer based on information included in the header of the packet, where the header includes information related to at least a destination of the data, an attribute of a memory access to the main storage and a length of the data. The transfer processor carries out a parallel process for each user process by making a data transfer between the main storage and the network in units of the packet depending on the attribute of the memory access.

Abstract: Any two of multiple processor elements are coupled with each other via a data communication network that has a definite communication buffer length and includes multiple communication buffers. A packet having a header and body is created using processed data, and then transferred by a transmitting unit. After sending the processed data, the transmitting unit transmits dummy data, having a body which is longer than the communication buffer length in the data communication network, to the same receiving station as the one to which the processed data is transmitted. The transmitting unit then guarantees a processor element serving as a receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of the dummy data.

Abstract: This invention relates to an abnormal packet processing system, and is directed to minimize processing of an abnormal packet during communication between a plurality of processing units by a receiving processor. This data processing system includes a plurality of processing units connected through an interconnection. At least one of the processing units is a transmitting processor which includes a unit for detecting an abnormality of a data packet during transmission of the data packet to a receiving processor; and a unit for adding abnormality report data to the data packet being transmitted and sending the data packet with the abnormality report data to the receiving processor, or, in the alternate, inhibiting transmission of the abnormal packet.

Abstract: In a multiprocessor system, transfer processing sections permit transfer of data and system information among a plurality of processors in order for the processors to perform parallel processing. The system includes physical processors within which virtual processors are realized and a plurality of logical processors corresponding to a plurality of processes to be processed. In transferring data and system information, each of the transfer processing sections selects a destination logical process number corresponding to a process to be transferred and reads from main storage physical processor and within-physical-processor virtual processor numbers corresponding to the logical processor number, data and system information for transfer toward a destination. In the destination, the physical or virtual processor executes the process.

Abstract: A multiprocessor system having a plurality of processors connected in parallel with each other through a network for performing mutual communication. Each processor includes a transfer queue unit for storing transfer requests, a main storage, a reception unit for receiving a transfer request from another processor, and a transmission unit for sending designated data to another processor when the transfer request is enqueued in the transfer queue unit. Each processor also includes a first register for storing information indicating whether the transfer queue unit is full, i.e. has an area available for storing a transfer request, and a second register for indicating whether a transfer request is a valid transfer request during a reception operation. A save unit is connected to the reception unit for temporarily saving a transfer request, and an enqueuing unit is provided for enqueuing a transfer request from the save unit to the transfer queue unit.