Patents by Inventor Kazushige Matsuyama

Kazushige Matsuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7939886
    Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: May 10, 2011
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Oshima, Masato Itoi
  • Publication number: 20090250750
    Abstract: A trench gate power MOSFET (1) of the present invention includes an n-type epitaxial layer (12), gates (18) and MOSFET cells. The gate (18) is disposed in a trench (14) formed in a surface of the n-type epitaxial layer (12). The MOSFET cell is formed on the surface of the n-type epitaxial layer (12) so as to be in contact with side surfaces of the trench (14). The trench gate power MOSFET (1) further includes a p-type isolation region (26) formed on the surface of the n-type epitaxial layer (12) and disposed between the MOSFET cells adjacent to each other in the extending direction of the trench (14) out of the MOSFET cells, and has a pn-junction diode formed between the p-type isolation region (26) and the n-type epitaxial layer (12). According to the trench gate power MOSFET (1) of the present invention, the increase of a diode leakage current with the elevation of temperature can be suppressed.
    Type: Application
    Filed: September 21, 2005
    Publication date: October 8, 2009
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Oshima, Masato Itoi
  • Patent number: 7573096
    Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: August 11, 2009
    Assignee: Shindengen Electric Manufacturing Co, Ltd.
    Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Ohshima, Masato Itoi
  • Publication number: 20080315301
    Abstract: A trench gate power MOSFET (1) includes: an n?-type epitaxial layer (12); a p-type body region (20) formed in the vicinity of an upper surface of the n?-type epitaxial layer (12); a plurality of trenches (14) formed so as to reach the n?-type epitaxial layer (12) from an upper surface of the p-type body region (20); and gates (18) formed in the trenches (14). In some regions facing the p-type body region (20) in the n?-type epitaxial layer (12), p-type carrier extracting regions (26a, 26b, 26c) are formed. According to the trench gate power MOSFET (1), holes generated in a cell region can be effectively collected through the p-type carrier extracting regions (26a, 26b, 26c) so as to further increase a speed of the switching operation.
    Type: Application
    Filed: November 22, 2005
    Publication date: December 25, 2008
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Oshima, Masato Itoi
  • Publication number: 20080135925
    Abstract: MOS FETs are formed by a drain layer 101, a drift layer 102, P-type body areas 103, N+-type source areas 105, gate electrodes 108, a source electrode film 110, and a drain electrode film 111. In parallel to the MOS FETs, the drain layer 101, the drift layer 102, the P?-type diffusion area 109, and the source electrode film 110 form a diode. The source electrode film 110 and the P?-type diffusion area 109 form an Ohmic contact. The total amount of impurities, which function as P-type impurities in each P-type body area 103, is larger than the total amount of impurities, which function as P-type impurities in the P?-type diffusion area 109.
    Type: Application
    Filed: February 16, 2005
    Publication date: June 12, 2008
    Inventors: Toshiyuki Takemori, Yuji Watanabe, Fuminori Sasaoka, Kazushige Matsuyama, Kunihito Ohshima, Masato Itoi