Patents by Inventor Kazushige Minegishi
Kazushige Minegishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5811872Abstract: A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on the first dielectrics film.Type: GrantFiled: January 31, 1996Date of Patent: September 22, 1998Assignee: Nippon Telegraph and Telephone CorporationInventors: Katsuyuki Machida, Katsumi Murase, Nobuhiro Shimoyama, Toshiaki Tsuchiya, Junichi Takahashi, Kazushige Minegishi, Yasuo Takahashi, Hideo Namatsu, Kazuo Imai
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Patent number: 5512513Abstract: A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on the first dielectrics film.Type: GrantFiled: August 25, 1994Date of Patent: April 30, 1996Assignee: Nippon Telegraph and Telephone CorporationInventors: Katsuyuki Machida, Katsumi Murase, Nobuhiro Shimoyama, Toshiaki Tsuchiya, Junichi Takahashi, Kazushige Minegishi, Yasuo Takahashi, Hideo Namatsu, Kazuo Imai
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Patent number: 5376590Abstract: A semiconductor device includes an interlevel film constituted by a first dielectrics film containing dangling bonds and a bonded group of Si and hydrogen, and a second dielectrics film formed on the first dielectrics film.Type: GrantFiled: January 19, 1993Date of Patent: December 27, 1994Assignee: Nippon Telegraph and Telephone CorporationInventors: Katsuyuki Machida, Katsumi Murase, Nobuhiro Shimoyama, Toshiaki Tsuchiya, Junichi Takahashi, Kazushige Minegishi, Yasuo Takahashi, Hideo Namatsu, Kazuo Imai
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Patent number: 4786954Abstract: A semiconductor memory device has a semiconductor substrate of one conductivity type in which a plurality of memory cells are formed, each of the plurality of memory cells including at least one capacitor and having a trench which is formed from one major surface of the semiconductor substrate so as to surround at least one memory cell, wherein a first insulating film having element isolation properties is formed on a bottom and most areas of side wall surfaces of the trench, a first conductive film serving as one electrode of the capacitor is formed on the side wall of the first insulating film and an exposed portion of the semiconductor substrate which is not covered with the first insulating film, a second insulating film is formed on the first conductive film, and a second conductive film serving as the other electrode of the capacitor is formed on the second insulating film.Type: GrantFiled: October 19, 1987Date of Patent: November 22, 1988Assignee: Nippon Telegraph & Telephone Public CorporationInventors: Takashi Morie, Kazushige Minegishi, Shigeru Nakajima
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Patent number: 4786953Abstract: A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.Type: GrantFiled: May 12, 1987Date of Patent: November 22, 1988Assignee: Nippon Telegraph & TelephoneInventors: Takashi Morie, Toshifumi Somatani, Shigeru Nakajima, Kazushige Minegishi, Kenji Miura
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Patent number: 4683643Abstract: A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.Type: GrantFiled: July 16, 1985Date of Patent: August 4, 1987Assignee: Nippon Telegraph and Telephone CorporationInventors: Shigeru Nakajima, Kazushige Minegishi, Kenji Miura, Takashi Morie, Toshifumi Somatani
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Patent number: 4672410Abstract: A semiconductor device has memory cells respectively located at intersections of bit and word lines arranged in a matrix form, each of the memory cells being constituted by a single insulated gate transistor and a single capacitor. One memory cell is formed in an element formation region defined by each of trenches arranged in a matrix form. The capacitor has an insulating film formed along part of a side wall surface of a trench formed in at least a direction of thickness of a semiconductor substrate and a conductive layer formed along the insulating film. The transistor has a gate insulating film adjacent to the capacitor and formed along a remaining portion of the side wall surface of the trench, a gate electrode formed along the gate insulating film, and a diffusion region formed in a major surface of the semiconductor substrate which is adjacent to the gate insulating film.Type: GrantFiled: July 9, 1985Date of Patent: June 9, 1987Assignee: Nippon Telegraph & TelephoneInventors: Kenji Miura, Shigeru Nakajima, Kazushige Minegishi, Takashi Morie, Toshifumi Somatani
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Patent number: 4645564Abstract: A semiconductor device with a metal-insulator-semiconductor capacitor has:a semiconductor substrate having a predetermined conductivity type and serving as one electrode of the metal-insulator-semiconductor capacitor, the semiconductor substrate being provided with a trench of a cross-sectionally rectangular shape which extends along a direction of thickness of the semiconductor substrate from a major surface thereof;a doped semiconductor layer formed along at least side wall surfaces of the trench, the semiconductor layer, which is formed by deposition and etching, being provided with an outer surface, starting to extend in a rounded shape from major surface portions of the semiconductor substrate and extending substantially parallel to the side wall surfaces of the trench, and a recess, which is defined by the semiconductor layer, having round corners at the bottom;a dielectric insulating layer formed on an exposed surface including the major surface of the semiconductor substrate and the outer surface of tType: GrantFiled: March 18, 1985Date of Patent: February 24, 1987Assignee: Nippon Telegraph & Telephone Public CorporationInventors: Takashi Morie, Kazushige Minegishi, Shigeru Nakajima
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Patent number: 4630237Abstract: A read-only memory has memory cells each with a vertical metal oxide semiconductor field effect transistor and a bit line. The vertical metal oxide semiconductor field effect transistor has a gate electrode serving as a word line, a source, a drain, and a vertical channel region between the source and drain constituted by first and second diffusion layers. The gate electrode is formed on a side wall of a trench, which has a pair of side walls substantially perpendicular to a major surface of a semiconductor substrate of a first conductivity type and an interconnecting bottom surface substantially perpendicular to the side wall surfaces. The first and second diffusion layers of a second conductivity type are formed in an upper portion of the semiconductor substrate and in a bottom of the trench, respectively. The bit lines are formed in a predetermined pattern.Type: GrantFiled: July 24, 1985Date of Patent: December 16, 1986Assignee: Nippon Telegraph & TelephoneInventors: Kenji Miura, Shigeru Nakajima, Kazushige Minegishi, Toshifumi Somatani, Takashi Morie, Tatsuo Baba