Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.

Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.

Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.

Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.

Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.

Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A memory controller includes a terminal to receive, from a processor, a request for access to a dynamic random access memory having a data storage area divided into a plurality of banks each divided into a plurality of pages. A memory control unit is also provided to activate a page to be accessed, based on said access request from said processor, and to execute, before a next request for access to a page to be accessed subsequently by said processor, precharge of said page to be accessed subsequently.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

Abstract: A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.

Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.