Patents by Inventor Kazushige Yamagishi

Kazushige Yamagishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9231717
    Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiko Hotta, Seiichi Saito, Kazushige Yamagishi
  • Publication number: 20150229419
    Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 13, 2015
    Inventors: Yoshihiko Hotta, Seiichi Saito, Kazushige Yamagishi
  • Patent number: 9036093
    Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshihiko Hotta, Seiichi Saito, Kazushige Yamagishi
  • Publication number: 20140241475
    Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.
    Type: Application
    Filed: May 7, 2014
    Publication date: August 28, 2014
    Applicant: Renesas Mobile Corporation
    Inventors: Yoshihiko Hotta, Seiichi Saito, Kazushige Yamagishi
  • Patent number: 8767131
    Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.
    Type: Grant
    Filed: February 15, 2013
    Date of Patent: July 1, 2014
    Assignee: Renesas Mobile Corporation
    Inventors: Yoshihiko Hotta, Seiichi Saito, Kazushige Yamagishi
  • Publication number: 20130242204
    Abstract: A semiconductor device includes a one-segment tuner I/F that is connected to a one-segment tuner, a tuner I/F that is connected to a digital terrestrial tuner, a decoder that selectively decodes a first broadcast signal supplied from the one-segment tuner I/F and a second broadcast signal supplied from the tuner I/F, a general purpose processor that is provided separately from the decoder and decodes the first broadcast signal, and a switch unit that, based on signal intensity of the second broadcast wave, switches the decoding by the decoder between the first broadcast signal and the second broadcast signal while the general purpose processor is decoding the first broadcast signal. The one-segment tuner I/F, the tuner I/F, the decoder, the general purpose processor, and the switch unit are integrated on one chip.
    Type: Application
    Filed: February 15, 2013
    Publication date: September 19, 2013
    Applicant: RENESAS MOBILE CORPORATION
    Inventors: Yoshihiko Hotta, Seiichi Saito, Kazushige Yamagishi
  • Patent number: 8332683
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: December 11, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Publication number: 20100180140
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Application
    Filed: March 25, 2010
    Publication date: July 15, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 7711976
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: July 13, 2007
    Date of Patent: May 4, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 7557809
    Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: July 7, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
  • Publication number: 20080168295
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Application
    Filed: July 13, 2007
    Publication date: July 10, 2008
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 7254737
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: August 7, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Publication number: 20050062749
    Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
    Type: Application
    Filed: November 9, 2004
    Publication date: March 24, 2005
    Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
  • Patent number: 6839063
    Abstract: The basic section of the multimedia data-processing system includes a CPU 1100, an image display unit 2100, a unified memory 1200, a system bus 1920, and devices 1300, 1400, and 1500 connected to the system bus. In this configuration, the CPU is formed on an LSI mounted on a single silicon wafer including instruction processing unit 1110 and display control unit 1140. Main storage area 1210 and display area 1220 are stored within the unified memory. Unified memory port 1910 for connecting the corresponding LSI and the unified memory is provided independently of the system bus intended to connect the LSI and the input/output devices. The unified memory port can be driven faster than system bus.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: January 4, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Yasuhiro Nakatsuka, Tetsuya Shimomura, Manabu Jyou, Yuichiro Morita, Takashi Hotta, Kazushige Yamagishi, Yutaka Okada
  • Publication number: 20040263523
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Application
    Filed: July 23, 2004
    Publication date: December 30, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Publication number: 20040193779
    Abstract: A memory controller includes a terminal to receive, from a processor, a request for access to a dynamic random access memory having a data storage area divided into a plurality of banks each divided into a plurality of pages. A memory control unit is also provided to activate a page to be accessed, based on said access request from said processor, and to execute, before a next request for access to a page to be accessed subsequently by said processor, precharge of said page to be accessed subsequently.
    Type: Application
    Filed: April 15, 2004
    Publication date: September 30, 2004
    Inventors: Yuichiro Morita, Manabu Jyou, Yasuhiro Nakatsuka, Tetsuya Shimomura, Yutaka Okada, Kazushige Yamagishi
  • Patent number: 6789210
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: September 7, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 6785833
    Abstract: A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: August 31, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Jun Satoh, Kazushige Yamagishi, Keisuke Nakashima, Koyo Katsura, Takashi Miyamoto, Mitsuru Watabe, Kenichiroh Ohmura
  • Patent number: 6744437
    Abstract: The present invention can be introduced to an architecture such as a personal computer or an amusement equipment for realizing a high-speed graphic processing. In the case where a frame buffer, a command memory and an image processor are integrated in one chip in order to improve the drawing performance of an image processing device, each of the frame buffer and the command memory is constructed by a plurality of identical memory modules and the same row address is allotted to each memory module, thereby increasing the memory address depth. Thereby, it is possible to realize an incorporated frame buffer and an incorporated command memory each of which has a large capacity when seen from the image processor.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: June 1, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Kazushige Yamagishi, Jun Sato, Takashi Miyamoto
  • Patent number: 6745279
    Abstract: A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read access to a page of the first bank, a second bank next to be accessed is precharged. In the case where a page mishit occurs due to the access from the first bank to the second bank by the graphic processing after the access to the first bank by the read operation, the memory controller activates the second bank immediately without precharging.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: June 1, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichiro Morita, Manabu Jyou, Yasuhiro Nakatsuka, Tetsuya Shimomura, Yutaka Okada, Kazushige Yamagishi