Patents by Inventor Kazushige Yazaki

Kazushige Yazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130073930
    Abstract: A predictor configured to predict a parity value of a Carry-Less multiplication result of a multiplicand data string and a multiplier data string being two data strings in which q (q is a natural number) data units being p-bit (p is a natural number equal to two or above) data, includes a unit configured to predict a parity value of a first data unit from lower order in a result data string representing the multiplication result based on a value and a parity value of a first data unit from lower order in each of the two data strings; and a unit configured to predict a parity value for data at a high-order p?1 bit of the result data string based on a value and a parity value for a q-th data unit from lower order in each of the two data strings.
    Type: Application
    Filed: August 30, 2012
    Publication date: March 21, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Kazushige Yazaki, Kenichi Kitamura