Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A semiconductor memory, including: a plurality of data terminals for transmitting data; a plurality of buffer circuits, each being coupled to a corresponding one of the data terminals; and a control circuit receiving an access command, that controls reading data from a memory cell array or writing data to the memory cell array, and a terminal setting information issued with each access command, and controlling the buffer circuits based on the access command and the terminal setting information, wherein, when the terminal setting information indicates a first mode, all of the buffer circuits function as input buffer circuits or output buffer circuits based on the access command, and wherein, when the terminal setting information indicates a second mode, a part of the buffer circuits functions as the input buffer circuits and a remaining part of the buffer circuits functions as the output buffer circuits.

Abstract: A semiconductor memory, including: a plurality of data terminals for transmitting data; a plurality of buffer circuits, each being coupled to a corresponding one of the data terminals; and a control circuit receiving an access command, that controls reading data from a memory cell array or writing data to the memory cell array, and a terminal setting information issued with each access command, and controlling the buffer circuits based on the access command and the terminal setting information, wherein, when the terminal setting information indicates a first mode, all of the buffer circuits function as input buffer circuits or output buffer circuits based on the access command, and wherein, when the terminal setting information indicates a second mode, a part, of the buffer circuits functions as the input buffer circuits and a remaining part of the buffer circuits functions as the output buffer circuits.

Abstract: A semiconductor memory includes: a plurality of input/output terminals that can be switched between being a plurality of common input/output terminals capable of bidirectionally transmitting data and a plurality of separate input/output terminals including a plurality of dedicated input terminals that receives data and a plurality of dedicated output terminals that outputs data; and a control circuit that switches the common input/output terminals and the separate input/output terminals based on input/output terminal setting information issued with each access command that controls reading from a memory cell or writing to the memory cell, the switched terminals being used to transmit data read out from the memory cell or data written to the memory cell according to the access command.

Abstract: A semiconductor memory includes: a plurality of input/output terminals that can be switched between being a plurality of common input/output terminals capable of bidirectionally transmitting data and a plurality of separate input/output terminals including a plurality of dedicated input terminals that receives data and a plurality of dedicated output terminals that outputs data; and a control circuit that switches the common input/output terminals and the separate input/output terminals based on input/output terminal setting information issued with each access command that controls reading from a memory cell or writing to the memory cell, the switched terminals being used to transmit data read out from the memory cell or data written to the memory cell according to the access command.

Abstract: A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Abstract: A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Abstract: This invention allows for stable operation of a circuit to which an output voltage is supplied. The invention resides in a semiconductor device comprising a VREF1 regulator to which a reference voltage Vref1 relative to a first potential is input; and an output circuit which generates an output voltage Vint that is proportional to a voltage on its input terminal relative to a second potential. The VREF1 regulator comprises a constant current source which generates a constant current having a current value that is proportional to the reference voltage Vref1; and a first resistor element which is supplied with the constant current, one end of which is coupled to the input terminal of the output circuit and the other end of which is coupled to the second potential.

Abstract: Provided is a duty detection circuit including: a first capacitor; a first transistor that controls charge or discharge currents of the first capacitor during a first period of a clock signal; a second capacitor; a second transistor that controls charge or discharge currents of the second capacitor during a second period of the clock signal; and a latch circuit that detects that a potential of one of the first capacitor and the second capacitor reaches a predetermined potential, and latches an output based on a result of the detection.

Abstract: A duty ratio correction circuit includes a clock input buffer that receives a first clock signal, a clock duty adjuster that adjusts a duty ratio of a second clock signal output from the clock input buffer based on a correction signal and generates a third clock signal, a data input buffer that receives a first data signal, a data duty adjuster that adjusts a duty ratio of a second data signal output from the data input buffer based on the correction signal and generates a third data signal, and a duty comparator that generates the correction signal based on the third clock signal.

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A level shift circuit of the invention includes a CMOS inverter circuit that receives an input pulse signal having a crest value of a first potential, a latch circuit that operates on a power supply of a second potential which is higher than the first potential, and a power supply circuit that supplies a power supply of not less than the first potential and less than the second potential to the CMOS inverter circuit. The latch circuit has one end thereof connected to an output end of the CMOS inverter circuit and outputs from the other end thereof an output pulse signal having a crest value of the second potential and a same phase as the input pulse signal. The power supply circuit functions to limit the power supply when the input pulse signal assumes at least the ground level.

Abstract: This invention allows for stable operation of a circuit to which an output voltage is supplied. The invention resides in a semiconductor device comprising a VREF1 regulator to which a reference voltage Vref1 relative to a first potential is input; and an output circuit which generates an output voltage Vint that is proportional to a voltage on its input terminal relative to a second potential. The VREF1 regulator comprises a constant current source which generates a constant current having a current value that is proportional to the reference voltage Vref1; and a first resistor element which is supplied with the constant current, one end of which is coupled to the input terminal of the output circuit and the other end of which is coupled to the second potential.

Abstract: A power supply circuit comprises: a first voltage booster circuit that receives a first clock signal having a fixed frequency, and supplies a voltage to a prescribed circuit; and a second voltage booster circuit that receives a second clock signal having a frequency corresponding to an operating frequency of the prescribed circuit, and supplies a voltage to the prescribed circuit.

Abstract: A duty ratio correction circuit includes a clock input buffer that receives a first clock signal, a clock duty adjuster that adjusts a duty ratio of a second clock signal output from the clock input buffer based on a correction signal and generates a third clock signal, a data input buffer that receives a first data signal, a data duty adjuster that adjusts a duty ratio of a second data signal output from the data input buffer based on the correction signal and generates a third data signal, and a duty comparator that generates the correction signal based on the third clock signal.

Abstract: Provided is a duty detection circuit including: a first capacitor; a first transistor that controls charge or discharge currents of the first capacitor during a first period of a clock signal; a second capacitor; a second transistor that controls charge or discharge currents of the second capacitor during a second period of the clock signal; and a latch circuit that detects that a potential of one of the first capacitor and the second capacitor reaches a predetermined potential, and latches an output based on a result of the detection.