Abstract: A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor substrate so as to expose extension region formation portions of the trench-type cell transistor region and a high breakdown voltage transistor region; forming extension regions in each region by performing ion implantation in the semiconductor substrate surface of the trench-type cell transistor region and the high breakdown voltage transistor region and then patterning gates, and forming extension regions of an ordinary breakdown voltage transistor by covering the trench-type cell transistor region and the high breakdown voltage transistor region with a photoresist layer and implanting ions in the ordinary breakdown voltage transistor region.

Abstract: A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor substrate so as to expose extension region formation portions of the trench-type cell transistor region and a high breakdown voltage transistor region; forming extension regions in each region by performing ion implantation in the semiconductor substrate surface of the trench-type cell transistor region and the high breakdown voltage transistor region and then patterning gates, and forming extension regions of an ordinary breakdown voltage transistor by covering the trench-type cell transistor region and the high breakdown voltage transistor region with a photoresist layer and implanting ions in the ordinary breakdown voltage transistor region.

Abstract: A semiconductor device comprising a recessed transistor coexists with P-N gate planar-type transistors, wherein high-concentration impurity-diffused material 9 is buried in a polysilicon film, which is the gate electrode of the recessed transistor, in order to suppress the reduction of ON current caused by a depletion phenomenon of the recessed gate of the recessed transistor, and to prevent increase in variation of the threshold voltage of the planar-type transistor composed of the P or N gate of a conductivity type different from the conductivity type of the recessed transistor.

Abstract: A semiconductor device includes: a semiconductor substrate; a pair of first diffusion layer regions provided near a top face of the semiconductor substrate; a channel region provided between the first diffusion layer regions of the semiconductor substrate; a gate insulation film provided on the channel region and on the semiconductor substrate such as to overlap with at least part of the first diffusion layer regions; a gate electrode provided on the insulation film; a pair of silicon selective growth layers provided on the semiconductor substrate at both sides of the gate electrode, each of the pair of silicon selective growth layers overlapping with at least part of the first diffusion layer regions, and being provided at a distance from the gate electrode; second diffusion layer regions provided in each of the silicon selective growth layers, peak positions of impurity concentration of the second diffusion layer regions being shallower than bottoms of the silicon selective growth layers; and third diffusio

Abstract: An objective of the present invention is to provide a more miniaturized semiconductor device while maintaining low-resist contact. A semiconductor device comprises transistors Tr1, Tr2, a first contact 13 and second contacts 10. The transistors Tr1, Tr2 are formed on a semiconductor substrate 1 and adjacent to each other. The first contact 13 is formed between the transistors Tr1, Tr2 in a self-alignment structure, connected to a common source to the transistors Tr1, Tr2 and contains a metal. The second contacts 10 are connected to the drains in the transistors Tr1, Tr2, respectively and contain a metal.

Abstract: A method of manufacturing a semiconductor device forms an N? diffusion layer to be a source/drain region of a grooved transistor simultaneously with an N? diffusion layer of a channel region directly under a gate electrode of an antifuse element. The formation of the N? diffusion layer directly under the gate electrode of the antifuse element stabilizes electrical connection between the gate electrode and the source/drain diffusion region even during writing with a low write voltage.

Abstract: An objective of the present invention is to provide a semiconductor device capable of suppressing generation of the hot carriers while reducing resistance in a drain region, and a method of manufacturing the same. Specifically, the present invention provides a semiconductor device including a field effect transistor comprising a source region and a drain region in the surface region of a semiconductor silicon substrate, characterized in that the drain region has a multiple impurity diffusion layer including at least a first conductivity type impurity diffusion layer and a second conductivity type impurity diffusion layer, and a bird's beak provided on the side of the drain region of the lower part of a gate electrode provided is larger than a bird's beak provided on the side of the source region of the lower part of the gate electrode.

Abstract: A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: In a semiconductor device (10), plural diffusion layer areas (2, 3) are formed so that the impurity concentration of the diffusion layer area (2) is set to be higher than that of the diffusion layer area (3), and a first contact wire (4) connected to the diffusion layer area (2) having the higher impurity concentration is set to be larger in sectional area than a second contact wire (5) connected to the diffusion layer area (3) having the lower impurity concentration.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: In a semiconductor device (10), plural diffusion layer areas (2, 3) are formed so that the impurity concentration of the diffusion layer area (2) is set to be higher than that of the diffusion layer area (3), and a first contact wire (4) connected to the diffusion layer area (2) having the higher impurity concentration is set to be larger in sectional area than a second contact wire (5) connected to the diffusion layer area (3) having the lower impurity concentration.

Abstract: In a process for forming a storage electrode having a number of hemi-spherical grains formed on a surface thereof, after a number of hemi-spherical grains are formed on a surface of the storage electrode, phosphorus or arsenic is ion-implanted to the hemi-spherical grains under an ion implantation energy of 20 keV to 50 keV.

Abstract: A semiconductor device including an IGFET (insulated gate field effect transistor) (30) is disclosed. IGFET (30) may include a source/drain area (15) having an impurity concentration distribution that may be formed shallower at a higher concentration than the impurity concentration distribution in another source/drain area (7). A gate oxide film may include a first gate oxide film (5) adjacent to source/drain area (7) and a second gate oxide film (12) adjacent to source drain area (15). Second gate oxide film (12) may be thinner than first gate oxide film (5). An impurity concentration distribution of a second channel impurity area (11) under second gate oxide film (12) may be at a higher concentration than an impurity concentration distribution of a first channel impurity area (9) under first gate oxide film (5). In this way, an electric field at a PN junction of source/drain area (7) may be reduced.

Abstract: In fabrication of a semiconductor memory device and especially a DRAM (dynamic random access memory) having an HSG-type stacked-capacitor structure, after a storage-node-forming silicon film has been surface-treated with an HSG preprocess using dilute fluoric acid, the storage-node-forming film on the sidewall surface of a storage-node-forming contact pattern at an accessory or alignment region is prevented from floating in the air and hence being peeled off, which would have lowered the yield. For this purpose, the storage-node-forming silicon film covers the sidewall surface of the contact pattern at the alignment region.

Abstract: In a process for forming a storage electrode having a number of hemi-spherical grains formed on a surface thereof, after a number of hemi-spherical grains are formed on a surface of the storage electrode, phosphorus or arsenic is ion-implanted to the hemi-spherical grains under an ion implantation energy of 20 keV to 50 keV.

Abstract: A packing bag is easy to open and allows an end of an content to be easily exposed to the outside by separating heat-bonding portions of external an internal packing films from each other and tearing the external packing film. The packing bag includes two rectangular packing films each having a thermoplastic resinous layer formed on its inner surface.

Abstract: In fabrication of a semiconductor memory device and especially a DRAM (dynamic random access memory) having an HSG-type stacked-capacitor structure, after a storage-node-forming silicon film has been surface-treated with an HSG preprocess using dilute fluoric acid, the storage-node-forming film on the sidewall surface of a storage-node-forming contact pattern at an accessory or alignment region is prevented from floating in the air and hence being peeled off, which would have lowered the yield. For this purpose, the storage-node-forming silicon film covers the sidewall surface of the contact pattern at the alignment region.

Abstract: In a semiconductor memory device with a stacked capacitor structure, a MOS transistor is formed on a substrate to have a gate electrode, a source region and a drain region. An insulating film is formed on the MOS transistor with an opening passing through the insulting film to one of the source and drain regions of the MOS transistor. A conductive storage electrode is formed such that it is connected to the one of the source and drain regions of the MOS transistor and has a first portion extending along a top surface of the insulating film and a second portion provided at each of edges of the first portion, and including a first subportion extending in an upper direction from an upper surface of the first portion and a second subportion below a lower surface of the first portion.