Patents by Inventor Kazutaka Masuzawa

Kazutaka Masuzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140091850
    Abstract: The present invention copes with fluctuations in a power supply voltage when a capacitor for coping with fluctuations in the power supply voltage has been omitted and also cases in which the power supply voltage is constantly low, thereby ensuring driving of an active element. A gate driving device of an IGBT includes: a first switch portion which turns on the IGBT; a second switch portion which turns off the IGBT; a current control portion which controls the outflow of charge on the gate to a ground line such that current is constant; a first protection circuit which suppresses outflow of gate current to the power supply line; and a second protection circuit which detects a prescribed fluctuation in an internal power supply voltage Vdc, and interrupts the connection between the current control portion and the ground line.
    Type: Application
    Filed: July 5, 2012
    Publication date: April 3, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takanori Kohama, Kazutaka Masuzawa
  • Patent number: 8217704
    Abstract: A gate drive device which can suppress the fluctuation of an internal power source voltage and output voltage, while reducing the number of parts by omitting a bypass capacitor connected in parallel with a semiconductor integrated circuit, is provided. The gate drive device drives the gate of an active element with a large input capacity, such as an IGBT or MOSFET, and includes a semiconductor integrated circuit. The semiconductor integrated circuit has an internal power source based on an external power source, such as a battery. The semiconductor integrated circuit incorporates a voltage drop suppressing circuit, configured so that, if an input external power source voltage momentarily drops below a minimum operating voltage, a drop of an internal power source voltage below the minimum operating voltage, and a sharp drop in a voltage output to the gate, are prevented by the voltage drop suppressing circuit.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: July 10, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takanori Kohama, Kazutaka Masuzawa, Naoki Kumagai
  • Publication number: 20100289562
    Abstract: A gate drive device which can suppress the fluctuation of an internal power source voltage and output voltage, while reducing the number of parts by omitting a bypass capacitor connected in parallel with a semiconductor integrated circuit, is provided. The gate drive device drives the gate of an active element with a large input capacity, such as an IGBT or MOSFET, and includes a semiconductor integrated circuit. The semiconductor integrated circuit has an internal power source based on an external power source, such as a battery. The semiconductor integrated circuit incorporates a voltage drop suppressing circuit, configured so that, if an input external power source voltage momentarily drops below a minimum operating voltage, a drop of an internal power source voltage below the minimum operating voltage, and a sharp drop in a voltage output to the gate, are prevented by the voltage drop suppressing circuit.
    Type: Application
    Filed: May 11, 2010
    Publication date: November 18, 2010
    Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.
    Inventors: Takanori Kohama, Kazutaka Masuzawa, Naoki Kumagai
  • Patent number: 6414773
    Abstract: In a transmission section (1), a light-emitting element (13) is driven by a digital signal (DS1) serving as an object of transmission, light emitted from the light-emitting element (13) is split by a beam splitter (17) into two linearly polarized light components which are orthogonal to each other, and the linearly polarized light components are radiated by ¼-wavelength plates (15A and 15C) into the air as circularly polarized light components having the same rotating direction.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: July 2, 2002
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Kazutaka Masuzawa, Mikio Aoki
  • Patent number: 5523622
    Abstract: For taking a characteristic impedance matching of signal transmission lines in a package which carries thereon a semiconductor chip with a very high-speed LSI formed thereon, there is provided a semiconductor integrated circuit device wherein one ends of signal transmission lines formed on a main surface of a package substrate are extended up to the position just under pads formed on a main surface of the semiconductor chip and are connected to the pads on the chip electrically through bump electrodes, while opposite ends of the signal transmission lines are extended to the outer peripheral portion of the main surface of the package substrate and outer leads are bonded thereto.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: June 4, 1996
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Takashi Harada, Kazuhiro Yoshihara, Kazutaka Masuzawa, Kiyoshi Hayashi, Jun Kumazawa, Kenji Nagai, Masahiko Nishiuma, Chiyoshi Kamada