Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: A display and an image displaying method which ensure gradation expression by a sub field system limits display resolution information in predetermined sub fields, excluding a lower sub field, thereby shortening an address control period. Further, noise dots originated from error diffusion is made less noticeable dot by dot by independently controlling the least significant sub field. This limits the amount of resolution information of a displayed image and improves the general image quality.

Abstract: A group of high order subfields and a group of low order subfields are provided, at least one independent control subfield is provided in the group of low order subfields and in other low order subfields, two lines are simultaneously addressed using the same data. Hereby, a display and an image displaying method wherein an address control period is reduced, using this surplus time, the luminance is enhanced, multiple gradations are provided or a pseudo contour interference is reduced, the resolution information of a displayed image is limited and synthetic image quality is enhanced are provided.

Abstract: A color image display apparatus which supplies red, green, and blue color video signals to respective red, green, and blue light emitting cells and performs color image display. Assuming that time response characteristics of light emission by red, green, and blue light emitting cells have respective values TR, TG, and TB, and |X| represents an absolute value of X, then |TR-TG|<|TR-TB| and |TR-TG|<|TG-TB| are satisfied. A front color fringe occurring at a front edge of a moving white rectangular pattern displayed on the color image display apparatus is blue and a rear color fringe occurring at a rear edge of the moving white rectangular pattern displayed on the color image display apparatus is yellow, thereby causing the front color fringe and the rear color fringe to be inconspicuous.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: A color image display apparatus which supplies red, green and blue color video signals to respective red, green and blue light emitting cells and performs color image display. Assuming that time response characteristics of light emission by red, green and blue light emitting cells have respective values TR, TG and TB, and |X| represents absolute value of X, then, |TR−TG|<|TR−TB | and |TR−TG|<|TG−TB| are satisfied.

Abstract: A display apparatus uses a sub field which illuminates addressed pixels of a display unit to display an image. The display apparatus includes an image signal processing circuit which performs sub field conversion processing on an input image signal, a computational processing circuit which arranges address data of at least one lower sub field of an image displayed on the display unit identical in plural lines, and a drive circuit which addresses and illuminates pixels of the display unit based on the outputs of the input signal processing circuit and the computational processing circuit. An image corresponding to the input image signal is displayed by driving the display unit with the drive circuit when the computational processing circuit performs addressing of the at least one lower sub field simultaneously in plural lines and address periods which select the illuminated pixels of said display unit are shortened.

Abstract: A color image display apparatus which supplies red, green, and blue color video signals to respective red, green, and blue light emitting cells and performs color image display. Assuming that time response characteristics of light emission by red, green, and blue light emitting cells have respective values TR, TG, and TB, and |X| represents an absolute value of X, then |TR-TG|<|TR-TB| and |TR-TG|<|TG-TB| are satisfied. A front color fringe occurring at a front edge of a moving white rectangular pattern displayed on the color image display apparatus is blue and a rear color fringe occurring at a rear edge of the moving white rectangular pattern displayed on the color image display apparatus is yellow, thereby causing the front color fringe and the rear color fringe to be inconspicuous.

Abstract: A display apparatus uses a sub field which illuminates addressed pixels of a display unit to display an image. The display apparatus includes an image signal processing circuit which performs sub field conversion processing on an input image signal, a computational processing circuit which arranges address data of at least one lower sub field of an image displayed on the display unit identical in plural lines, and a drive circuit which addresses and illuminates pixels of the display unit based on the outputs of the input signal processing circuit and the computational processing circuit. An image corresponding to the input image signal is displayed by driving the display unit with the drive circuit when the computational processing circuit performs addressing of the at least one lower sub field simultaneously in plural lines and address periods which select the illuminated pixels of said display unit are shortened.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an AID converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of White-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: A group of high order subfields and a group of low order subfields are provided, at least one independent control subfield is provided in the group of low order subfields and in other low order subfields, two lines are simultaneously addressed using the same data. Hereby, a display and an image displaying method wherein an address control period is reduced, using this surplus time, the luminance is enhanced, multiple gradations are provided or a pseudo contour interference is reduced, the resolution information of a displayed image is limited and synthetic image quality is enhanced are provided.

Abstract: This specification and drawings disclose a display technology which displays an image by illuminating pixels of a display unit. The apparatus comprises an image signal processing circuit which processes an input image signal, a control circuit which controls display resolution information relating to the image displayed on the display unit, and a drive circuit which drives the display unit based on the output of an input signal processing circuit and the control circuit. The display resolution information is limited by the control circuit, and an image corresponding to an input image signal is displayed on the display unit when a time during which illuminated pixels are selected on the display unit, is shortened.

Abstract: A display and an image displaying method which ensure gradation expression by a sub field system limits display resolution information in predetermined sub fields, excluding a lower sub field, thereby shortening an address control period. Further, noise dots originated from error diffusion is made less noticeable dot by dot by independently controlling the least significant sub field. This limits the amount of resolution information of a displayed image and improves the general image quality.

Abstract: There is provided an inexpensive display apparatus of high image quality which conducts video signal display of high resolution by using liquid crystal panels of low resolution. Four liquid crystal panels corresponding to R, G and B basic pixels as well as W (white) pixels are used. The additional W pixels are shifted from the R, G and B basic pixels so as to form a quincunx pattern, and optical combining is conducted. As for low resolution information, full color display using basic pixels is conducted. As for high resolution information exceeding this, only luminance information is displayed by using white pixels obtained by combining the R, G and B basic pixels and using the additional W pixels.

Abstract: A display apparatus for displaying an image having gradation represented by subfields. The display apparatus includes a display panel, a circuit for outputting information in which a plurality of subfields in one field period is arranged so as to have first plural array portions where allotted light emitting weights increase gradually and second plural array portions where allotted light emitting weights decrease gradually, and a driver for forming a drive signal based on the information and for outputting the drive signal to the display panel.

Abstract: A video signal processor for outputting a video signal based on an output horizontal synchronizing signal and an output vertical synchronizing signal. The processor includes a circuit inputting a reference horizontal synchronizing signal, a circuit inputting a reference vertical synchronizing signal, a circuit generating an output horizontal synchronizing signal having a frequency different from that of the reference horizontal synchronizing signal, and a circuit generating an output vertical synchronizing signal synchronized in phase with the reference vertical synchronizing signal.

Abstract: In a color image display apparatus, assuming that time response characteristics of light emission by red, green and blue light emitting cells have values TR, TG and TB, the difference between the values TR and TG is less than that between the values TR and TB and that between the values TG and TB. The apparatus has a subfield arrangement including a portion where a light emitting weight gradually decreases and a portion where the light emitting weight gradually increases, or a subfield arrangement to obtain a plurality of light emission peaks in one field.

Abstract: In a video signal processing device, an input video signal VO representing a test pattern having two gradations of black and white is converted to 8-bit data by an A/D converter 4 in synchronism with sampling clocks generated in a write-in control circuit 5, and then stored in a memory 6. An MPU 9 reads out picture element data in an effective area of the video signal stored in the memory 6, and calculates the difference AT between the average value of white-level picture element data whose values are larger than a predetermined value and the average value of black-level picture element data whose values are smaller than a predetermined value, and the total variance VT between the variance of the white-level picture element data and the variance of the black-level picture element data. The MPU 9 controls the phase of the sampling clocks generated in the write-in control circuit 5 so that the AT is maximum and the VT is minimum.

Abstract: A video signal processor which includes a circuit for converting the number of lines in a digitized video signal, a circuit for generating a display dot clock, a circuit for outputting analog pixel data subjected to a line number conversion and having a frequency different from that of the display dot clock, and a circuit for smoothing the analog pixel data; and in which a frequency fck of the display dot clock, an output frequency frk of the analog pixel data and a frequency fho of the horizontal synchronization signal satisfies an equation;frck/N=fck/M=fhowhere M and N are natural numbers satisfying M.noteq.N.

Abstract: A CRT display device capable of displaying a signal from the existing image signal source, in which a vertical frequency is approximately fixed and a horizontal frequency is widely distributed beyond a ratio of 3:1, on one image screen. The CRT display device includes a scan converter unit and a display unit. The scan converter unit includes an output horizontal frequency unifying circuit, a horizontal blanking period ratio converting circuit, a vertical frequency converting unit and a vertical blanking period ratio converting circuit. The display unit includes a vertical deflection circuit and a circuit for correcting a vertical S-shaped distortion. In a phase synchronous circuit, a lock-out detector is connected to an output of a three state output digital phase detector, and on the basis of an output thereof, a switch is subjected to the "ON"/"OFF" control.