Patents by Inventor Kazutaka Narita

Kazutaka Narita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240327639
    Abstract: A binder resin for electrodes consisting of a polyimide-based resin having a melting point of 300° C. or lower, an electrode mixture paste including the binder resin for electrodes, an electrode active material, and a solvent; and an electrode including an electrode mixture layer including the binder resin for electrodes and an electrode active material; and a method for producing the electrode.
    Type: Application
    Filed: June 14, 2024
    Publication date: October 3, 2024
    Inventors: Takeshige Nakayama, Kazutaka Narita, Shohei Inoue
  • Patent number: 11898009
    Abstract: A flexible electronic device containing a polyimide film exhibiting excellent C-V characteristics. The polyimide film is a film that shows a maximum gradient of 0.005/V or more in a capacitance-voltage measurement of a laminate in which a polyimide film having a film thickness of 0.75 ?m is formed on a silicon wafer having a resistance value of 4 ?cm; the maximum gradient meaning a maximum value of an absolute value of a gradient in a normalized capacity-voltage curve during a third scan of forward direction scans; a capacity-voltage curve being measured by applying a direct current voltage is to the polyimide film with respect to the silicon wafer between a lowest voltage V1 and a highest voltage V2, and measuring capacitance while the direct current voltage is scanned in a forward direction and scanned in a negative direction; the normalized capacity-voltage curve being normalized so that the capacity at the lowest voltage V1 is 1.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: February 13, 2024
    Assignee: Ube Corporation
    Inventors: Norio Miura, Kazutaka Narita
  • Publication number: 20220166025
    Abstract: A polyimide-based binder for power storage device having a repeated breaking energy retention ratio of 70% or more. The use of the binder enables improvement of a power storage device having a high capacity.
    Type: Application
    Filed: March 27, 2020
    Publication date: May 26, 2022
    Inventors: Takeshige NAKAYAMA, Kazutaka NARITA
  • Publication number: 20210171714
    Abstract: A flexible electronic device containing a polyimide film exhibiting excellent C-V characteristics. The polyimide film is a film that shows a maximum gradient of 0.005N or more in a capacitance-voltage measurement of a laminate in which a polyimide film having a film thickness of 0.75 ?m is formed on a silicon wafer having a resistance value of 4 ?cm; the maximum gradient meaning a maximum value of an absolute value of a gradient in a normalized capacity-voltage curve during a third scan of forward direction scans; a capacity-voltage curve being measured by applying a direct current voltage is to the polyimide film with respect to the silicon wafer between a lowest voltage V1 and a highest voltage V2, and measuring capacitance while the direct current voltage is scanned in a forward direction and scanned in a negative direction; the normalized capacity-voltage curve is being normalized so that the capacity at the lowest voltage V1 is 1.
    Type: Application
    Filed: April 19, 2019
    Publication date: June 10, 2021
    Inventors: Norio MIURA, Kazutaka NARITA
  • Publication number: 20200407593
    Abstract: A polyimide precursor resin composition for forming a flexible device substrate, including a polyamic acid having a structure obtained from a tetracarboxylic acid component including at least one of 3,3?,4,4?-biphenyltetracarboxylic dianhydride and pyromellitic dianhydride, a diamine component including at least one of paraphenylene diamine and 4,4?-diaminodiphenyl ether, and a carboxylic acid monoanhydride, the polyamic acid satisfying equations (1) and (2) below: 0.97?X/Y<1.00??Equation (1) 0.5?(Z/2)/(Y?X)?1.05??Equation (2) in which X represents a number of moles of tetracarboxylic acid component, Y represents a number of moles of diamine component, and Z represents a number of moles of the carboxylic acid monoanhydride.
    Type: Application
    Filed: December 27, 2018
    Publication date: December 31, 2020
    Inventors: Norio MIURA, Kazutaka NARITA, Takeshige NAKAYAMA
  • Publication number: 20200172731
    Abstract: A binder resin for electrodes consisting of a polyimide-based resin having a melting point of 300° C. or lower, an electrode mixture paste including the binder resin for electrodes, an electrode active material, and a solvent; and an electrode including an electrode mixture layer including the binder resin for electrodes and an electrode active material; and a method for producing the electrode.
    Type: Application
    Filed: August 6, 2018
    Publication date: June 4, 2020
    Inventors: Takeshige NAKAYAMA, Kazutaka NARITA, Shohei INOUE
  • Publication number: 20190232333
    Abstract: Disclosed is a method for producing a polyimide laminate, the method including the steps of applying a polyimide precursor solution onto a substrate and heating the polyimide precursor solution, to thereby form a polyimide film layer on the substrate. The substrate is any plate selected from a glass plate, a metal plate, and a ceramic plate. The heating step includes irradiation with far infrared rays using an infrared heater that generates a maximum radiant energy at an infrared wavelength of 3.5 to 6 ?m. The highest heating temperature is preferably 350 to 550° C. The time required to increase the temperature from 180 to 280° C. during a temperature-increasing process is preferably 2 minutes or longer.
    Type: Application
    Filed: July 14, 2017
    Publication date: August 1, 2019
    Inventors: Kazutaka NARITA, Takeshige NAKAYAMA, Naoki KITAYAMA, Shohei INOUE
  • Publication number: 20160207229
    Abstract: In an embodiment, a film retainer 200 includes a base member 210 fixed to a tenter chain and a pin plate 220 supported on the base member 210 to be movable in the movement direction of the tenter chain. The pin plate 220 is provided with a plurality of protruding pins 230 that are stuck into the film for holding the film. The film retainer for a tenter apparatus is capable of suppressing a bowing phenomenon without significant modifications to an existing manufacture facility and being applicable under arbitrary manufacture conditions.
    Type: Application
    Filed: August 14, 2014
    Publication date: July 21, 2016
    Applicant: UBE Industries, Ltd.
    Inventors: Hiroyuki IKEUCHI, Gouhei YAMAMOTO, Kazutaka NARITA
  • Patent number: 5159260
    Abstract: This reference voltage generator device detects a voltage corresponding to an energy gap of a semiconductor, or a voltage of a value close thereto, or a voltage based on an energy level of a semiconductor, and generates the detected voltage as a reference voltage. The reference voltage is generated by detecting a difference of threshold voltages of first and second insulated gate field-effect transistors (IGFETs). Gate electrodes of the first and second IGFETs are formed on gate insulating films which are formed on different surface areas of an identical semiconductor substrate under substantially the same conditions. The gate electrodes of the first and second IGFETs are respectively made of two semiconductors which are selected from among a semiconductor of a first conductivity type, a semiconductor of a second conductivity type and an intrinsic semiconductor made of an identical semiconductor material, and which have Fermi energy levels of values different from each other.
    Type: Grant
    Filed: January 7, 1987
    Date of Patent: October 27, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Kanji Yoh, Osamu Yamashiro, Satoshi Meguro, Koichi Nagasawa, Kotaro Nishimura, Harumi Wakimoto, Kazutaka Narita
  • Patent number: 4167018
    Abstract: A MIS capacitance element formed in a semiconductor substrate of p-(or n-) conductivity type comprises an n- (or p-) type well region formed in one principal surface of the semiconductor substrate and a polycrystalline region formed on the surface of the well region through a gate insulator layer. A polar voltage is applied between the well region and the polycrystalline layer so that the well region is forward biased and no carrier channel region is formed in the surface of the well region. The MIS element is particularly suited for use in a complementary MIS IC and provides almost no voltage or field dependency of the capacitance.
    Type: Grant
    Filed: February 23, 1977
    Date of Patent: September 4, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Ohba, Kazutaka Narita