Patents by Inventor Kazutaka ONISHI

Kazutaka ONISHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11977362
    Abstract: In the conventional distributed control system, since each control device updates the data area at a timing when a control packet is received, in a case where there is a difference in communication delay between the control devices or in a case where the communication delay includes jitter, it is difficult to match the contents of data in all the control devices in a case of focusing on a certain moment during system operation. Therefore, depending on the start timing of a control application, the control application operates on the basis of different data between the control devices, thus limiting control performance improvement. Accordingly, time slots on the network are allocated according to the result of a calculation unit, and a cyclic memory synchronization update unit synchronizes the timing of reflecting data in the input/output and the cyclic memory and the timing of using data of a cyclic memory.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 7, 2024
    Assignee: HITACHI, LTD.
    Inventors: Tatsuya Maruyama, Yusaku Otsuka, Hidenori Omiya, Toshiki Shimizu, Iori Kobayashi, Kazutaka Onishi, Noritaka Matsumoto
  • Patent number: 11734201
    Abstract: In a control system including one or more control nodes and one or more I/O nodes connected to one or more devices and communicable with the control nodes, the control nodes execute at least one control program on a first OS, and the I/O nodes execute at least one I/O program on a second OS with higher punctuality. The control program generates a control command based on state control set in advance for the device and transmits the control command to the I/O node. The I/O program stores the control command received from the control node in a storage unit, and executes processing related to the device according to the control command stored in the storage unit.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: August 22, 2023
    Assignee: HITACHI, LTD.
    Inventors: Kazutaka Onishi, Yusaku Otsuka, Tatsuya Maruyama
  • Publication number: 20230098444
    Abstract: In a control system including one or more control nodes and one or more I/O nodes connected to one or more devices and communicable with the control nodes, the control nodes execute at least one control program on a first OS, and the I/O nodes execute at least one I/O program on a second OS with higher punctuality. The control program generates a control command based on state control set in advance for the device and transmits the control command to the I/O node. The I/O program stores the control command received from the control node in a storage unit, and executes processing related to the device according to the control command stored in the storage unit.
    Type: Application
    Filed: October 9, 2020
    Publication date: March 30, 2023
    Inventors: Kazutaka ONISHI, Yusaku OTSUKA, Tatsuya MARUYAMA
  • Publication number: 20220382235
    Abstract: In the conventional distributed control system, since each control device updates the data area at a timing when a control packet is received, in a case where there is a difference in communication delay between the control devices or in a case where the communication delay includes jitter, it is difficult to match the contents of data in all the control devices in a case of focusing on a certain moment during system operation. Therefore, depending on the start timing of a control application, the control application operates on the basis of different data between the control devices, thus limiting control performance improvement. Accordingly, time slots on the network are allocated according to the result of a calculation unit, and a cyclic memory synchronization update unit synchronizes the timing of reflecting data in the input/output and the cyclic memory and the timing of using data of a cyclic memory.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 1, 2022
    Inventors: Tatsuya MARUYAMA, Yusaku OTSUKA, Hidenori OMIYA, Toshiki SHIMIZU, Iori KOBAYASHI, Kazutaka ONISHI, Noritaka MATSUMOTO