Patents by Inventor Kazutaka Osawa

Kazutaka Osawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240068861
    Abstract: A counting scale includes a weighing pan, a weighing sensor connected to the weighing pan, a storage unit including a registered data table storing, as registered data, a unique identification number, an article name, and a unit weight with respect to one article, an arithmetic processing unit configured to urge placement of one piece of the target article on the weighing pan, calculate a unit weighed value of the one piece of the target article from the weighing sensor, narrow down registered data including a unit weight within a predetermined range with respect to the unit weighed value as candidate data from the registered data table, and obtain sorted candidate data by selecting and sorting the candidate data in ascending order of absolute value of deviation from the unit weighed value, and a display unit configured to display the sorted candidate data.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 29, 2024
    Inventors: Toshihiko OSAWA, Kazutaka SUGA
  • Publication number: 20230378228
    Abstract: A radiation detector comprising: a pixel array in which pixels each having a radiation detection element configured to convert radiation into charges and an amplification transistor configured to amplify a signal from the radiation detection element and output the amplified signal are arrayed in a matrix shape; and signal wiring provided for each pixel column, wherein the signal wiring does not overlap an active layer, in which the amplification transistor is arranged, in a plan view.
    Type: Application
    Filed: May 12, 2023
    Publication date: November 23, 2023
    Inventors: KAZUTAKA OSAWA, TAKANORI WATANABE, TOMONA YAMAGUCHI
  • Publication number: 20230375722
    Abstract: A radiation detector comprising: a pixel array in which pixels each having a radiation detection element configured to convert radiation into charges and an amplification transistor configured to amplify a signal from the radiation detection element and output the amplified signal are arrayed in a matrix shape; and signal wiring provided for each pixel column, wherein a pixel isolation structure formed to surround the radiation detection element in a plan view is provided, and the amplification transistor is arranged inside a region defined by the pixel isolation structure in a plan view.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 23, 2023
    Inventors: KAZUTAKA OSAWA, TAKANORI WATANABE, TOMONA YAMAGUCHI
  • Patent number: 11600055
    Abstract: An apparatus includes an extract unit configured to extract features of a first image based on an electromagnetic wave in a first frequency band, an acquire unit configured to acquire motion information about the features, a classify unit configured to classify the features into a first group and a second group based on the motion information, and a remove unit configured to remove, from the first image, a signal corresponding to the feature belonging to the first group.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 7, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Kazutaka Osawa, Takahiro Sato, Takeaki Itsuji, Nao Nakatsuji, Mayu Ishikawa
  • Publication number: 20210312202
    Abstract: An apparatus includes an extract unit configured to extract features of a first image based on an electromagnetic wave in a first frequency band, an acquire unit configured to acquire motion information about the features, a classify unit configured to classify the features into a first group and a second group based on the motion information, and a remove unit configured to remove, from the first image, a signal corresponding to the feature belonging to the first group.
    Type: Application
    Filed: March 25, 2021
    Publication date: October 7, 2021
    Inventors: Kazutaka Osawa, Takahiro Sato, Takeaki Itsuji, Nao Nakatsuji, Mayu Ishikawa
  • Patent number: 7690944
    Abstract: A connector assembly, for electrically connecting electrical cables 7 to a test head 4, comprises a plurality of types of cable side connectors 8 respectively attached to one end of the electrical cable 7; and a intermediate connector 6 to which the plurality of types of cable side connectors 8 are connected in a detachable manner, and the intermediate connector 6 having a first engagement part 501 having a shape with which all types of cable side connectors 8 can be engaged and an output terminal 602 able to be engaged with a test head side connector 41 electrically connected to a pin electronics board of the test head 4.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: April 6, 2010
    Assignees: Advantest Corporation, Tyco Electronics Japan G.K.
    Inventors: Shigeru Matsumura, Kazutaka Osawa, Hiroyuki Hama, Yuichiro Izumi, Eiichiro Takemasa
  • Patent number: 7611377
    Abstract: An interface apparatus 5 mounted on a test head 4 comprises: an electrical cable 54 having one end electrically connected to a socket board 66; a device side connector 541 attached to the other end of the electrical cable 54; and a intermediate connector 53 electrically connecting a test head side connector 41 provided on the test head 4 and the device side connector 541 and the intermediate connector 53 having a connector body 531 provided at a bottommost part of the interface apparatus 5; an engagement hole 532 provided at the connector body 531 and having the device side connector 541 detachably connected to it; and an output terminal 537 provided at the connector body 531 and having the test head side connector 41 detachably connected to it.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: November 3, 2009
    Assignee: Advantest Corporation
    Inventors: Shigeru Matsumura, Kazutaka Osawa, Hiroyuki Hama, Yuichiro Izumi
  • Publication number: 20080076298
    Abstract: A connector assembly, for electrically connecting electrical cables 7 to a test head 4, comprises a plurality of types of cable side connectors 8 respectively attached to one end of the electrical cable 7; and a intermediate connector 6 to which the plurality of types of cable side connectors 8 are connected in a detachable manner, and the intermediate connector 6 having a first engagement part 501 having a shape with which all types of cable side connectors 8 can be engaged and an output terminal 602 able to be engaged with a test head side connector 41 electrically connected to a pin electronics board of the test head 4.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 27, 2008
    Inventors: Shigeru Matsumura, Kazutaka Osawa, Hiroyuki Hama, Yuichiro Izumi, Eiichiro Takemasa
  • Publication number: 20080076297
    Abstract: An interface apparatus 5 mounted on a test head 4 comprises: an electrical cable 54 having one end electrically connected to a socket board 66; a device side connector 541 attached to the other end of the electrical cable 54; and a intermediate connector 53 electrically connecting a test head side connector 41 provided on the test head 4 and the device side connector 541 and the intermediate connector 53 having a connector body 531 provided at a bottommost part of the interface apparatus 5; an engagement hole 532 provided at the connector body 531 and having the device side connector 541 detachably connected to it; and an output terminal 537 provided at the connector body 531 and having the test head side connector 41 detachably connected to it.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 27, 2008
    Applicant: ADVANTEST Corporation
    Inventors: Shigeru Matsumura, Kazutaka Osawa, Hiroyuki Hama, Yuichiro Izumi
  • Patent number: 5761216
    Abstract: A bit error measurement system provides means for generating test patterns, multiplexing means and means for specifying and recording a pattern position. In a first aspect, a bit error measurement system has a pattern generator having M channels of pattern generation and a pattern generation controller 10 for controlling the pattern generation in the M channels so that when one channel is selected to generate a pattern the other channels are controlled to be waiting. In a second aspect, a clock frequency difference detector 150 is provided for counting a frequency of an input clock 111 and comparing the results with the frequency at the time of previous switching to detect whether the frequency change is greater than a predetermined value to judge whether the system is in a measurement state and to permit or prohibit a switching operation of a clock switch circuit.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: June 2, 1998
    Assignee: Advantest Corp.
    Inventors: Tetsuo Sotome, Takayuki Nakajima, Kazutaka Osawa, Kazuhiro Shimawaki, Kouichi Shiroyama