Abstract: According to one embodiment, a memory system includes a memory and controller. The controller repeatedly performs an erase voltage application process for data stored in a target area in the memory. The controller performs an erase verification process for determining whether the erase is successful using erase verification voltage. The controller determines whether an erase time is longer than a first threshold value. The controller sets the target area to a use prohibition state when the erase time is longer than the first threshold value.

Abstract: According to one embodiment, a memory system includes a memory device and a controller. The controller is configured to make the memory device apply a first verify voltage to a first word line for determining whether writing of a first data value into a first cell transistor has been completed. The controller is configured to make the memory device apply a second verify voltage to a second word line for determining whether writing of the first data value into a second cell transistor has been completed. The second verify voltage is different from the first verify voltage.

Abstract: According to one embodiment, a control system includes: a memory device; and a controller. The memory device includes a first cell transistor. The controller is configured to store information on a first temperature associated with a temperature of the memory device upon a write of data in the first cell transistor, obtain a second temperature of the memory device, determine an adjustment from adjustments based on a combination of the first temperature and the second temperature, and instruct the memory device to use for a first parameter a first value and a value which is based on the determined adjustment to read data from the first cell transistor.

Abstract: A semiconductor memory device includes a nonvolatile memory and a controller. The nonvolatile memory has a plurality of memory cells that are connected to word lines to which a read voltage is applied at the time of reading data stored in the memory cells. The controller is configured to determine a read voltage for a target memory cell by selecting a tracking parameter based on a word line connected to the target memory cell and an elapsed time from a previous access to a group of memory cells including the target memory cell, and executing a tracking process on the memory cells also connected to the word line connected to the target memory cell using the selected tracking parameter.

Abstract: A memory system includes a semiconductor memory chip including a substrate, an array of memory cells in arranged each of a plurality of levels in a thickness direction of the substrate, and a plurality of word lines arranged in the thickness direction, each of the word lines being connected to memory cells in one of the levels, and a controller. The controller is configured to determine an offset value with respect to each of a plurality of word line groups that are organized from the plurality of word lines along the thickness direction, and, with respect to each of the word line groups, set a voltage to be applied to the word line group during at least one of write, read, and erase operations, based on a base parameter value and the offset value corresponding to the word line group.

Abstract: According to one embodiment, a memory system monitors at least one of an erasing time length and a programming time length of each of physical blocks included in a logical block among a plurality of logical blocks. The memory system disassembles a first logical block among the plurality of logical blocks when both of a first physical block and a second physical block exist in the first logical block, the first physical block having an erasing time length or a programming time length falling within a first range, and the second physical block having an erasing time length or a programming time length falling outside the first range.

Abstract: According to one embodiment, a magnetic recording medium including a substrate and a magnetic recording layer formed on the substrate and including a plurality of projections is obtained. The array of the plurality of projections includes a plurality of domains in which the projections are regularly arranged, and a boundary region between the domains, in which the projections are irregularly arranged. The boundary region is formed along a perpendicular bisector of a line connecting the barycenters of adjacent projections.

Abstract: According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.

Abstract: A memory system includes a nonvolatile memory a controller that controls the nonvolatile memory, and a backup power supply. In response to a detection that power from an external source to the memory system is interrupted, at which time power to the memory system starts to be supplied from the backup power supply, the controller transmits a first command to the nonvolatile memory to change a parameter for a write operation and then transmits a second command to the nonvolatile memory to carry out a write operation, such that the nonvolatile memory carries out the write operation using the changed parameter.

Abstract: A perpendicular magnetic recording medium according to an embodiment includes a substrate and perpendicular magnetic recording layer. The perpendicular magnetic recording layer includes a recording portion and non-recording portion. The recording portion has patterns regularly arranged in the longitudinal direction, and includes magnetic layers containing Fe or Co and Pt as main components, and at least one additive component selected from Ti, Si, Al, and W. The non-recording portion includes oxide layers formed by oxidizing the side surfaces of the magnetic layers, and nonmagnetic layers formed between the oxide layers.

Abstract: A semiconductor memory device includes a semiconductor memory chip including a plurality of regions of memory cells, including a first memory region and a second memory region, and a memory controller configured to carry out a read of a memory cell in the first memory region by applying a first read voltage, and a read of a memory cell in the second memory region by applying a second read voltage that is different from the first read voltage.

Abstract: According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.

Abstract: According to one embodiment, a memory device includes a controller, and a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, the erase operation executing every block, the nonvolatile memory transferring a first reply showing a completion of the erase operation and a fail bit count showing a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller. The controller selects a target block as a target of the erase operation based on the fail bit count.

Abstract: According to one embodiment, a memory device includes a controller, and a nonvolatile memory controlled by the controller, the nonvolatile memory executing an erase operation by an algorithm which repeats loops, each loop including an erase step applying an erase pulse to a memory cell and a verify step verifying a threshold voltage of the memory cell after the erase step, an erase-verify-read voltage using the verify step changing in a x-th loop (x is a natural number equal to or larger than 2). The controller is capable of changing a value of x, and indicates the value of x to the nonvolatile memory.

Abstract: A semiconductor memory device includes a semiconductor memory chip including a plurality of regions of memory cells, including a first memory region and a second memory region, and a memory controller configured to carry out a read of a memory cell in the first memory region by applying a first read voltage, and a read of a memory cell in the second memory region by applying a second read voltage that is different from the first read voltage.

Abstract: A perpendicular magnetic recording medium according to an embodiment includes a substrate and perpendicular magnetic recording layer. The perpendicular magnetic recording layer includes a recording portion and non-recording portion. The recording portion has patterns regularly arranged in the longitudinal direction, and includes magnetic layers containing Fe or Co and Pt as main components, and at least one additive component selected from Ti, Si, Al, and W. The non-recording portion includes oxide layers formed by oxidizing the side surfaces of the magnetic layers, and nonmagnetic layers formed between the oxide layers.

Abstract: According to one embodiment, there is provided a method for forming a pattern including forming an island-like metal underlayer comprised of a first metal, a phase-separated release layer including a first metal, a second metal, and a metal oxide, a mask layer, and a resist layer on a processed layer in this order, forming a concave-convex pattern on the resist layer, transferring the pattern to the mask layer, the phase-separated release layer, and the processed layer in this order, dissolving the phase-separated release layer using a peeling liquid for dissolving the first metal and the second metal, and removing the mask layer from the processed layer to expose the concave-convex pattern.

Abstract: According to one embodiment, a memory system comprises a first nonvolatile semiconductor memory, a temperature sensor and a controller. The first nonvolatile semiconductor memory includes the first and second semiconductor chips. The temperature sensor detects a temperature of the first nonvolatile semiconductor memory. The controller acquires the wear level per block of the first and second semiconductor chips based on the temperature of the first nonvolatile semiconductor memory and the frequency of use of the first nonvolatile semiconductor memory, and sets, based on the wear level, an examination frequency for defining a cycle of examination of quality of data per block of the first and second semiconductor chips.

Abstract: According to one embodiment, a perpendicular magnetic recording medium is provided, which includes a non-magnetic granular underlayer formed on a substrate and containing metal grains of a first metal and a grain boundary layer surrounding the metal grains, each metal grain including a projection projecting from the boundary layer and a bottom portion embedded in the grain boundary layer, and a contact angle of the edge of the projection to the surface of the grain boundary layer being 45° to 85°, a non-magnetic intermediate layer formed on a surface of each projection and a magnetic recording layer having a projection pattern formed on the basis of a pattern of the projections in the non-magnetic intermediate layer via the non-magnetic intermediate layer.

Abstract: According to one embodiment, a pattern formation method includes steps of forming a layer to be processed on a substrate, forming a metal microparticle layer by coating the layer to be processed with a metal microparticle coating solution containing metal microparticles and a solvent, reducing a protective group amount around the metal microparticles by first etching, forming a protective layer by exposing the substrate to a gas containing C and F and adsorbing the gas around the metal microparticles to obtain a projection pattern, and transferring the projection pattern to the layer to be processed by second etching.