Abstract: A semiconductor memory device has a reference section which includes a first reference cell block and second reference cell blocks. The first reference cell block includes a second contact diffusion region which is arranged under a virtual ground line and is connected to this virtual ground line via a contact hole. The second reference cell blocks include first and third contact diffusion regions which are arranged under a bit line and can be connected to the bit line via contact holes as needed. Thereby, the number of reference cell blocks to be connected in series can be selected freely, allowing finer settings of a reference current value.

Abstract: A non-volatile semiconductor device stores multi-value information of at least two bits in one memory cell. A source region and a drain region serve as diffusion regions. A first channel region and a second channel region are placed between the source region and the drain region. A first gate electrode is arranged over the first channel region and the drain region. A second gate electrode is arranged over the second channel region and the source region. The first channel region stores a first threshold value while the second channel region stores a second threshold value different from the first threshold value.

Abstract: In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed.

Abstract: In a semiconductor memory device, a memory cell array 108 and a GND selector circuit 107 arranged in the vicinity of the memory cell array are connected via a metal wiring. In the GND selector circuit 107, a single transistor is connected to a single line of the metal wiring. A GND selecting transistor in the GND selector circuit 107 is also used as a precharge selecting transistor. The memory cell array 108 and a Y selector circuit 110 arranged in the vicinity of the memory cell array are connected via a digit line. In the Y selector circuit 110, a single digit-selecting transistor is connected to a single digit line. The digit-selecting transistor is also used as a precharge selecting transistor.

Abstract: In a semiconductor memory, four bit line diffused interconnections 1 connected to two bit line terminals D0 and D1 through bank selection transistors BT1 and BT2 are connected to drains of memory cells of four column pairs, respectively, and four bit line diffused interconnections 2 connected to one virtual ground line terminal VG1 through bank selection transistors BT3 to BT6 are connected to sources of memory cells of the four column pairs. The bank selection transistors BT1 to BT6 are so located that each of the bit line diffused interconnections 1 is connected to a corresponding one of the bit line terminals D0 and D1 through only one bank selection transistor and each of bit line diffused interconnections 2 is connected to the virtual ground line terminal VG1 through only one bank selection transistor. Thus, data can be surely read from a selected memory cell at a high speed.