Abstract: A first and second semiconductor memory circuits and a redundant circuit for realizing a defect relief function are made connectable, whereby the redundant circuit is shared between the two semiconductor memory circuits, and when a failure occurs in either of the semiconductor memory circuits, the redundant circuit operates as a portion in the semiconductor memory circuit. Consequently, the defect relief function can be added to each of the two semiconductor memory circuits by only adding one redundant circuit and redundant changeover switch groups.

Abstract: A semiconductor device includes two latch circuits, each of which latches a corresponding one of complementary data outputs supplied from an amplifier circuit, and includes only one intervening gate from an input thereof to an output thereof, the latch circuits being reset by an activation signal that activates the amplifier circuit.

Abstract: A first and second semiconductor memory circuits and a redundant circuit for realizing a defect relief function are made connectable, whereby the redundant circuit is shared between the two semiconductor memory circuits, and when a failure occurs in either of the semiconductor memory circuits, the redundant circuit operates as a portion in the semiconductor memory circuit. Consequently, the defect relief function can be added to each of the two semiconductor memory circuits by only adding one redundant circuit and redundant changeover switch groups.

Abstract: A semiconductor memory device includes a row decoder selecting a row, word lines that extend from the row decoder and are connected to memory cells, a dummy word line that extends from starting ends of the word lines substantially in parallel therewith and returns to the starting ends in which the dummy word line is folded back in an intermediate position of a total length of the word lines, and a sense amplifier that amplifies data read from a memory cell coupled to a selected one of the word lines at a timing defined by a signal propagated along the dummy word line.

Abstract: A semiconductor device includes two latch circuits, each of which latches a corresponding one of complementary data outputs supplied from an amplifier circuit, and includes only one intervening gate from an input thereof to an output thereof, the latch circuits being reset by an activation signal that activates the amplifier circuit.

Abstract: A semiconductor memory device includes a row decoder selecting a row, word lines that extend from the row decoder and are connected to memory cells, a dummy word line that extends from starting ends of the word lines substantially in parallel therewith and returns to the starting ends in which the dummy word line is folded back in an intermediate position of a total length of the word lines, and a sense amplifier that amplifies data read from a memory cell coupled to a selected one of the word lines at a timing defined by a signal propagated along the dummy word line.

Abstract: According to the present invention, a synchronization circuit, which receives a plurality of input signals and a sync signal and performs a predetermined operation corresponding to said input signals in synchronization with said sync signal, comprising: a transition detector for detecting each transition of said plurality of input signals and for generating transition detection signal indicating that said transition occurs; and an internal sync signal generator for, upon the receipt of said sync signal, supplying an internal sync signal to said synchronization circuit when said detection signal indicate that said transition occurs, and for ceasing to supply said internal sync signal to said synchronization circuit, regardless of whether said sync signal is received, when said transition detection signal does not indicate that said transition occurs. According to the present invention, power consumption accompanying an unwanted, repeated operation can be eliminated.

Abstract: The drive circuit of the present invention includes a signal generation circuit which generates a drive signal at a specific timing. A first driver circuit drives one end of a first wire connected to a plurality of controlled circuits in response to the drive signal. A second driver circuit drives one end of a second wire having a smaller drive load than the first wire in response to the drive signal. A high speed driver circuit has its inputs connected to the other end of the second wire and to the other end of the first wire, and has an output terminal that drives the other end of the first wire when the voltage level at the other end of the second wire does not coincide with the voltage level at the other end of the first wire.

Abstract: An object of the present invention is to provide a MOS static RAM in which the power consumption can be reduced when it is required to reduce the power consumption during standby, and sufficient soft error resistance can be secured when it is required to provide sufficient soft error resistance for the cell. A MOS static RAM of the present invention comprises a power supply circuit for generating a plurality of voltages of different voltage values and a selection circuit for selecting one voltage from among the plurality of voltages output from the power supply circuit and supplying the selected voltage as a cell data retention voltage to a flip-flop that forms a cell.

Abstract: An object of the present invention is to provide a MOS static RAM in which the power consumption can be reduced when it is required to reduce the power consumption during standby, and sufficient soft error resistance can be secured when it is required to provide sufficient soft error resistance for the cell. AMOS static RAM of the present invention comprises a power supply circuit for generating a plurality of voltages of different voltage values and a selection circuit for selecting one voltage from among the plurality of voltages output from the power supply circuit and supplying the selected voltage as a cell data retention voltage to a flip-flop that forms a cell.

Abstract: A power circuit is suitable for inclusion into a semiconductor apparatus, for example, and follows up the noise caused by the operation of an internal load circuit. When the voltage V.sub.DD applied to the internal circuit changes a relatively moderate amount due to such causes as the variation of an externally supplied power supply voltage V.sub.CC or the operation of the internal circuit, a negative feedback is applied to a variable resistance element by a voltage comparator and a variable resistance element driver. In response to an instantaneous variation of the internal circuit applied voltage V.sub.DD, the variation being caused by the operation of the internal circuit 100, for example, a rapid negative feedback is applied to the variable resistance element by a capacitor.

Abstract: A constant voltage generator circuit comprises adjusting means for making fine adjustment of each back-gate voltage of transistors on the basis of external control signals, and a transistor circuit for outputting a constant voltage adjusted on the basis of the back-gate voltage. A constant voltage generator circuit comprises adjusting means for making fine adjustment of each back-gate voltage of transistors on the basis of external control signals; and a transistor circuit for outputting a constant voltage adjusted on the basis of the back-gate voltages, the transistor circuit including a plurality of N transistors with their respective gates and sources connected together, and a load element for dividing the power source voltage with a plurality of N transistors.

Abstract: A semiconductor memory device includes a reset circuit for equalizing potentials of a pair of signal lines for transferring a complementary signal, and a clock generating circuit generating a first clock signal and a second clock signal at a time different from the generation of the first clock. A logical OR gate circuit generates a reset signal based on the first and second clock signals.When the pulse width of an active low chip selection signal is shorter than a predetermined time period, the pulse width of the reset signal is made longer than that generated when the pulse width of the signal is longer than the predetermined time period. As a result, the potentials of a pair of complementary bit lines connected to each cell in the memory cell array can be reliably reset, and the delay time in the access operation can be reduced.