Patents by Inventor Kazuto KANOMATA

Kazuto KANOMATA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10483957
    Abstract: The present invention provides a semiconductor device capable of properly performing equalization even when the transfer rate of serial data is changed. A semiconductor device includes: an addition circuit of adding input data and feedback data and outputting addition data; a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data; a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data; a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and a calibration circuit of adjusting a delay time since the first sampling circuit outputs the sampling data until the addition data corresponding to the output sampling data is supplied to the first sampling circuit.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuto Kanomata
  • Publication number: 20180083607
    Abstract: The present invention provides a semiconductor device capable of properly performing equalization even when the transfer rate of serial data is changed. A semiconductor device includes: an addition circuit of adding input data and feedback data and outputting addition data; a first sampling circuit of sampling the addition data from the addition circuit and outputting sampling data; a multiplication circuit of multiplying the sampling data from the first sampling circuit by a tap coefficient to generate the feedback data; a tap coefficient determination circuit determining the tap coefficient on the basis of the sampling data from the first sampling circuit; and a calibration circuit of adjusting a delay time since the first sampling circuit outputs the sampling data until the addition data corresponding to the output sampling data is supplied to the first sampling circuit.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 22, 2018
    Inventor: Kazuto KANOMATA