Patents by Inventor Kazuto Saitoh

Kazuto Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6731004
    Abstract: An electronic device and method of making same wherein the device includes a substrate (e.g., a printed wiring board or semiconductor chip) having a circuit thereon, a first non-photosensitive layer (e.g., polyimide resin) positioned on the substrate and over the substrate's circuit, a second, photosensitive layer (e.g., epoxy resin) positioned on the first layer, and an electrically conductive layer positioned on the first, non-photosensitive layer and electrically coupled to the circuit through a hole in the first layer.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: May 4, 2004
    Assignee: International Business Machines Corporation
    Inventor: Kazuto Saitoh
  • Publication number: 20010004134
    Abstract: An electronic device and method of making same wherein the device includes a substrate (e.g., a printed wiring board or semiconductor chip) having a circuit thereon, a first non-photosensitive layer (e.g., polyimide resin) positioned on the substrate and over the substrate's circuit, a second, photosensitive layer (e.g., epoxy resin) positioned on the first layer, and an electrically conductive layer positioned on the first, non-photosensitive layer and electrically coupled to the circuit through a hole in the first layer.
    Type: Application
    Filed: December 11, 2000
    Publication date: June 21, 2001
    Inventor: Kazuto Saitoh
  • Patent number: 6229220
    Abstract: To provide a bump structure for soldering by forming a solder layer on the chip surface while keeping the space between a package substrate and a semiconductor chip large. Form a bump structured in double layers at a chip 1 and connect it to an electrode 11 of a package substrate 10 by soldering. The lower layer 3a in the double-layer structure does not fuse in soldering, and a definite distance between the substrate and the chip can be maintained. The upper layer 3b actually fuses in soldering and operates to electrically connect the bump to the electrode on the package substrate. The melting point of the lower layer is preferably at least 20° C. higher than that of the upper layer.
    Type: Grant
    Filed: September 11, 1996
    Date of Patent: May 8, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kazuto Saitoh, Reijiro Shoji
  • Patent number: 6093964
    Abstract: A metal bump structure constituted by forming a second metal layer on a first metal layer is used which meets the conditions that the first metal layer is not melted at the time of reflow heating for connecting a substrate with a semiconductor chip and the second metal layer is made of a metal producing no composition causing the reliability to deteriorate between the second metal layer and a solder portion formed on the substrate at the time of reflow heating for connecting the substrate with the semiconductor chip.
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: July 25, 2000
    Assignee: International Business Machines Corporation
    Inventor: Kazuto Saitoh