Patents by Inventor Kazuto Watanabe
Kazuto Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240096694Abstract: A conductive hard mask layer can be patterned with peripheral discrete openings. An anisotropic etch process can be performed to form peripheral discrete via cavities, which are subsequently expanded to form a continuous moat trench. An edge seal structure can be formed in the continuous moat trench. Alternatively, a conductive bridge structure may be formed prior to formation of a patterned conductive hard mask layer, and a moat trench can be formed around a periphery of the semiconductor die while the conductive bridge structure provides electrical connection between an inner portion and an outer portion of the conductive hard mask layer. The entire conductive hard mask layer can be electrically connected to a semiconductor substrate to reduce or prevent arcing during an anisotropic etch process that forms the peripheral discrete via cavities or the moat trench.Type: ApplicationFiled: September 16, 2022Publication date: March 21, 2024Inventor: Kazuto WATANABE
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Patent number: 11812598Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, a laterally perforated support pillar structure vertically extending through the alternating stack and the retro-stepped dielectric material portion, and a layer contact via structure laterally surrounded by the laterally perforated support pillar structure and contacting a top surface of a topmost electrically conductive layer within an area of the laterally perforated support pillar structure. Each electrically conductive layer within the area of the laterally perforated support pillar structure extends through the lateral openings.Type: GrantFiled: June 23, 2021Date of Patent: November 7, 2023Assignee: SANDISK TECHNOLOGIES LLCInventor: Kazuto Watanabe
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Publication number: 20230276625Abstract: Contact via openings are formed through a retro-stepped dielectric material portion in a three-dimensional memory device to underlying etch stop structures. The etch stop structures may include a stepped conductive or semiconductor etch stop plate overlying stepped surfaces in the staircase region. The contact via openings are extended through the etch stop structures. Alternatively, electrically conductive layers, including a topmost dummy electrically conductive layer in the staircase region, may be employed as etch stop structures. In this case, the contact via openings can be extended through the electrically conductive layers. Insulating spacers are formed at peripheral regions of the extended contact via openings. Contact via structures surrounded by the insulating spacers are formed in the extended contact via openings to a respective underlying electrically conductive layer.Type: ApplicationFiled: February 28, 2022Publication date: August 31, 2023Inventors: Kazuto WATANABE, Youko FURIHATA
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Patent number: 11569139Abstract: A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.Type: GrantFiled: March 8, 2021Date of Patent: January 31, 2023Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Ikue Yokomizo, Michiaki Sano, Kazuto Watanabe, Hajime Yamamoto, Takashi Yamaha, Koichi Ito, Katsuya Kato, Ryo Hiramatsu, Hiroshi Sasaki, Akihiro Tobioka, Liang Li
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Publication number: 20220415907Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, a laterally perforated support pillar structure vertically extending through the alternating stack and the retro-stepped dielectric material portion, and a layer contact via structure laterally surrounded by the laterally perforated support pillar structure and contacting a top surface of a topmost electrically conductive layer within an area of the laterally perforated support pillar structure. Each electrically conductive layer within the area of the laterally perforated support pillar structure extends through the lateral openings.Type: ApplicationFiled: June 23, 2021Publication date: December 29, 2022Inventor: Kazuto WATANABE
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Publication number: 20220285234Abstract: A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.Type: ApplicationFiled: March 8, 2021Publication date: September 8, 2022Inventors: Ikue YOKOMIZO, Michiaki SANO, Kazuto WATANABE, Hajime YAMAMOTO, Takashi YAMAHA, Koichi ITO, Katsuya KATO, Ryo HIRAMATSU, Hiroshi SASAKI, Akihiro TOBIOKA, Liang LI
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Patent number: 11249398Abstract: A method for producing a plated shaped structure, includes applying a photosensitive resin composition on a substrate to form a photosensitive resin coating film. The photosensitive resin composition includes: (A) a resin whose solubility in alkali is capable of being increased by an action of an acid; (B) a photoacid generator; and (C) a compound which is capable of being decomposed by an action of an acid to form a primary or secondary amine. The photosensitive resin coating film is exposed to light. The photosensitive resin coating film is developed after the exposing to light to form a resist pattern. A plating process is performed using the resist pattern as a mask.Type: GrantFiled: September 4, 2019Date of Patent: February 15, 2022Assignee: JSR CORPORATIONInventors: Hirokazu Sakakibara, Hirokazu Itou, Tomoyuki Matsumoto, Kazuto Watanabe
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Publication number: 20200321324Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.Type: ApplicationFiled: April 2, 2019Publication date: October 8, 2020Inventors: Michiaki Sano, Takashi YAMAHA, Koichi ITO, Ikue YOKOMIZO, Ryo HIRAMATSU, Kazuto WATANABE, Katsuya KATO, Hajime YAMAMOTO, Hiroshi SASAKI
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Patent number: 10797035Abstract: A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.Type: GrantFiled: April 2, 2019Date of Patent: October 6, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Michiaki Sano, Takashi Yamaha, Koichi Ito, Ikue Yokomizo, Ryo Hiramatsu, Kazuto Watanabe, Katsuya Kato, Hajime Yamamoto, Hiroshi Sasaki
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Patent number: 10790296Abstract: A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.Type: GrantFiled: May 21, 2019Date of Patent: September 29, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Takashi Yamaha, Katsuya Kato, Kazuto Watanabe, Hajime Yamamoto, Michiaki Sano, Koichi Ito, Ikue Yokomizo, Ryo Hiramatsu, Hiroshi Sasaki
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Publication number: 20190391489Abstract: A method for producing a plated shaped structure, includes applying a photosensitive resin composition on a substrate to form a photosensitive resin coating film. The photosensitive resin composition includes: (A) a resin whose solubility in alkali is capable of being increased by an action of an acid; (B) a photoacid generator; and (C) a compound which is capable of being decomposed by an action of an acid to form a primary or secondary amine. The photosensitive resin coating film is exposed to light. The photosensitive resin coating film is developed after the exposing to light to form a resist pattern. A plating process is performed using the resist pattern as a mask.Type: ApplicationFiled: September 4, 2019Publication date: December 26, 2019Applicant: JSR CorporationInventors: Hirokazu Sakakibara, Hirokazu Itou, Tomoyuki Matsumoto, Kazuto Watanabe
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Patent number: 10309382Abstract: A piston compressor may prevent excessive oil from accumulating in a crank chamber while securing the supply of oil to a swash plate. In a piston compressor in which an oil separation passage is formed in a shaft and a crank chamber communicates with a suction chamber through the oil separation passage, a supply passage opens at a region of a cylinder block opposed to a swash plate to allow a working fluid introduced from a discharge chamber into the crank chamber to be supplied to the swash plate and a bypass passage allowing the crank chamber to constantly communicate with the suction chamber is provided to prevent the accumulation of excessive oil in the crank chamber regardless of the operation condition. The bypass passage communicates with the crank chamber at a region positioned in the outer side of a rotation trajectory of the swash plate in the radial direction.Type: GrantFiled: June 26, 2015Date of Patent: June 4, 2019Assignee: Valeo Japan Co., Ltd.Inventors: Takanori Teraya, Katsumi Sakamoto, Kazuto Watanabe, Masayuki Kono
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Patent number: 10217746Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electricType: GrantFiled: January 11, 2018Date of Patent: February 26, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Tae-Kyung Kim, Raghuveer S. Makala, Yanli Zhang, Hiroyuki Kinoshita, Daxin Mao, Jixin Yu, Yiyang Gong, Kazuto Watanabe, Michiaki Sano, Haruki Urata, Akira Takahashi
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Patent number: 10211215Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. Each of the first insulating layers and the first sacrificial material layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion. Memory stack structures are formed through the horizontally-extending portions of the alternating stack. Regions of the non-horizontally-extending portions of the sacrificial material layers are masked with patterned etch mask portions. Unmasked first regions of the non-horizontally-extending portions of the first sacrificial material layers are selectively recessed, and the sacrificial material layers with electrically conductive layers. Each electrically conductive layer can include a vertical plate region and a protrusion region that protrudes above the vertical plate region and having a narrower lateral dimension that the vertical plate region.Type: GrantFiled: February 13, 2018Date of Patent: February 19, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Yashushi Ishii, Kazuto Watanabe, Michiaki Sano, Haruki Urata, Akira Takahashi, Tae-Kyung Kim
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Patent number: 10181442Abstract: A three-dimensional memory device includes an alternating stack of L-shaped insulating layers and L-shaped electrically conductive layers located over a top surface of a substrate, such that each of the L-shaped insulating layers and the L-shaped electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the alternating stack that includes the horizontally-extending portions of the L-shaped electrically conductive layers, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel, dielectric spacers non-horizontally extending between neighboring pairs of a non-horizontally-extending portion of an L-shaped insulating layer and a non-horizontally-extending portion of an L-shaped electrically conductive layer, and contact via structures that contact a respective one of the non-horizontally-extending portions of the L-shapedType: GrantFiled: November 30, 2017Date of Patent: January 15, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Kazuto Watanabe, Michiaki Sano, Haruki Urata, Akira Takahashi
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Patent number: 9809489Abstract: A composition for forming a conductive film includes at least one of a metal salt (A1) and a metal particle (A2) as component (A) that serves as a metal source of the conductive film, and a metalloxane compound (B). The metal salt (A1) and the metal particle (A2) contain one or more metals selected from the group consisting of Ni, Pd, Pt, Cu, Ag, and Au. The metalloxane compound (B) has at least one metal atom selected from the group consisting of Ti, Zr, Sn, Si, and Al in its main chain. Preferably, the metal salt (A1) is a carboxylate containing a metal selected from the group consisting of Cu, Ag, and Ni. Preferably, the metal particle (A2) has an average particle diameter of 5 nm to 100 nm and comprises a metal selected from the group consisting of Cu, Ag, and Ni.Type: GrantFiled: September 10, 2015Date of Patent: November 7, 2017Assignee: JSR CorporationInventors: Sugirou Shimoda, Kenzou Ookita, Keisuke Satou, Kazuto Watanabe
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Publication number: 20170122300Abstract: To provide a piston compressor capable of preventing excessive oil from accumulating in a crank chamber in any operation state while securing the supply of oil to a swash plate. In a piston compressor in which an oil separation passage (43) is formed in a shaft (7) and a crank chamber (2) communicates with a suction chamber (31) through the oil separation passage (43), a supply passage (40) opens at a region of a cylinder block (1) opposed to a swash plate (18) to thereby allow a working fluid introduced from a discharge chamber (32) into the crank chamber (2) to be supplied to the swash plate (18) and a bypass passage (50) allowing the crank chamber (2) to constantly communicate with the suction chamber (31) is provided to thereby prevent the accumulation of excessive oil in the crank chamber (2) regardless of the operation condition.Type: ApplicationFiled: June 26, 2015Publication date: May 4, 2017Applicant: Valeo Japan Co., Ltd.Inventors: Takanori Teraya, Katsumi Sakamoto, Kazuto Watanabe, Masayuki Kono
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Patent number: 9543201Abstract: In a method for forming a three-dimensional interconnection, a contact plug is formed within a through hole provided in a substrate and an upper wire formed on an upper side of the substrate and a lower wire formed on a lower side are electrically connected to one another by the contact plug. A coating film is formed on an upper surface of the substrate and inner surface of the through hole by applying a metal film-forming composition containing at least one salt of and a particle of a metal to the substrate provided with the through hole. A metal film is formed by heating the coating film, and plated by filling up the through hole by depositing a conductor on the metal film by a plating process using the metal film as a seed layer. An excess conductor deposited in the plating is removed by a chemical mechanical polishing process.Type: GrantFiled: August 26, 2015Date of Patent: January 10, 2017Assignee: JSR CorporationInventors: Kenzou Ookita, Isao Aritome, Keisuke Kuriyama, Taichi Matsumoto, Kazuto Watanabe, Atsushi Kobayashi, Sugirou Shimoda
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Publication number: 20160081189Abstract: A composition for forming a conductive film includes at least one of a metal salt (A1) and a metal particle (A2) as component (A) that serves as a metal source of the conductive film, and a metalloxane compound (B). The metal salt (A1) and the metal particle (A2) contain one or more metals selected from the group consisting of Ni, Pd, Pt, Cu, Ag, and Au. The metalloxane compound (B) has at least one metal atom selected from the group consisting of Ti, Zr, Sn, Si, and Al in its main chain. Preferably, the metal salt (A1) is a carboxylate containing a metal selected from the group consisting of Cu, Ag, and Ni. Preferably, the metal particle (A2) has an average particle diameter of 5 nm to 100 nm and comprises a metal selected from the group consisting of Cu, Ag, and Ni.Type: ApplicationFiled: September 10, 2015Publication date: March 17, 2016Applicant: JSR CorporationInventors: Sugirou SHIMODA, Kenzou OOKITA, Keisuke SATOU, Kazuto WATANABE
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Publication number: 20160064280Abstract: In a method for forming a three-dimensional interconnection, a contact plug is formed within a through hole provided in a substrate and an upper wire formed on an upper side of the substrate and a lower wire formed on a lower side are electrically connected to one another by the contact plug. A coating film is formed on an upper surface of the substrate and inner surface of the through hole by applying a metal film-forming composition containing at least one salt of and a particle of a metal to the substrate provided with the through hole. A metal film is formed by heating the coating film, and plated by filling up the through hole by depositing a conductor on the metal film by a plating process using the metal film as a seed layer. An excess conductor deposited in the plating is removed by a chemical mechanical polishing process.Type: ApplicationFiled: August 26, 2015Publication date: March 3, 2016Applicant: JSR CorporationInventors: Kenzou OOKITA, Isao Aritome, Keisuke Kuriyama, Taichi Matsumoto, Kazuto Watanabe, Atsushi Kobayashi, Sugirou Shimoda