Abstract: A semiconductor integrated circuit device provided with a SRAM realizing low power consumption and high speed is to be provided. Out of memory circuits which cause a timing generator circuit which selects writable and readable memory cells with the address selector circuit, conveys write signals to a memory cell selected by a write circuit, conveys read signals from a memory cell selected by a read circuit, and receives a clock signal, to generate operational timing signals to be conveyed to an address selector circuit, a write circuit and a read circuit, a circuit in which the operational timing is not too tight is configured of a higher threshold voltage MOSFET than the MOSFETs of other circuits.

Abstract: To a first signal line to which a signal with a comparable small amplitude against the power supply voltage is transmitted at a first timing, a second signal line to which a voltage maintained at a constant is transmitted at the first timing is laid out on the same wiring layer as that of the first signal line adjacently to each other. Thereby, the invention reduces the coupling noises without impairing a high density of the signal wirings, and provides a semiconductor integrated circuit device with a memory circuit that realizes a high integration, low power consumption, and high speed.

Abstract: A semiconductor integrated circuit device provided with a SRAM realizing low power consumption and high speed is to be provided. Out of memory circuits which cause a timing generator circuit which selects writable and readable memory cells with the address selector circuit, conveys write signals to a memory cell selected by a write circuit, conveys read signals from a memory cell selected by a read circuit, and receives a clock signal, to generate operational timing signals to be conveyed to an address selector circuit, a write circuit and a read circuit, a circuit in which the operational timing is not too tight is configured of a higher threshold voltage MOSFET than the MOSFETs of other circuits.

Abstract: A signal to be written is transmitted to said pairs of writing signal lines in parallel with address input operation for the selection of a word line, information stored in the memory cell selected in response to the selection operation of said word line is transmitted to said pair of reading signal lines via said second selecting switch circuit so that it is amplified by said sense amplifier, and the amplified output of said sense amplifier is compared with the signal to be written on said pair of writing signal lines so that the signal to be written is written into said selected memory cell by selectively turning on said first selecting switch circuit in response to a result of said comparison.

Abstract: There is provided a semiconductor integrated circuit device which can select the cache memory operation as required in which the priority is given to high speed operation or to low power consumption. In this circuit device, a set associative type cache memory includes read amplifier units for data-ways to provide a first operation mode for selecting an output from the data-way in relation to the cache hit state through the activation by giving limitation only to the read amplifier unit of the data-way in relation to the cache bit and a second operation mode for selecting an output from the data-way in relation to the cache hit without limitation on the read amplifiers to be activated. Selection of above operation mode is programmable depending on the setting of mode bit.

Abstract: To a first signal line to which a signal with a comparable small amplitude against the power supply voltage is transmitted at a first timing, a second signal line to which a voltage maintained at a constant is transmitted at the first timing is laid out on the same wiring layer as that of the first signal line adjacently to each other. Thereby, the invention reduces the coupling noises without impairing a high density of the signal wirings, and provides a semiconductor integrated circuit device with a memory circuit that realizes a high integration, low power consumption, and high speed.

Abstract: A signal to be written is transmitted to said pairs of writing signal lines in parallel with address input operation for the selection of a word line, information stored in the memory cell selected in response to the selection operation of said word line is transmitted to said pair of reading signal lines via said second selecting switch circuit so that it is amplified by said sense amplifier, and the amplified output of said sense amplifier is compared with the signal to be written on said pair of writing signal lines so that the signal to be written is written into said selected memory cell by selectively turning on said first selecting switch circuit in response to a result of said comparison.