Abstract: A nonvolatile semiconductor memory device of the present invention includes: a plurality of memory blocks each including a memory array including a plurality of memory cells, a plurality of word lines and bit lines provided so as to cross each other for selecting the memory cell, a row decoder for selecting the word line according to an externally-input row address signal, a column decoder for selecting the bit line according to an externally-input column address signal; and at least one internal voltage generation circuit for applying a voltage required for performing data write/erase operations on the memory array, a plurality of first switch circuits are provided such that each first switch circuit is provided between the at least one internal voltage generation circuit and the row decoder or the column decoder, and a switch selection circuit is provided for selectively operating the plurality of first switch circuits.

Abstract: A nonvolatile semiconductor storage device, comprising: a plurality of memory blocks, and at least one high voltage generation circuit, wherein the high voltage generation circuit is formed by a plurality of stages of basic pump cells, each basic pump cell including, a voltage increasing capacitor, an equalizing transistor connected to a voltage of a previous basic pump cell stage, a capacitor for increasing a voltage at a gate of the equalizing transistor, and a transistor which connects the voltage of the previous basic pump cell stage to the gate of the equalizing transistor, the nonvolatile semiconductor storage device further comprises, a discharge circuit connected to a node in the high-voltage generation circuit which has a high voltage, for discharging the node to a potential equal to or lower than a power supply voltage when the high-voltage generation circuit is stopped, and a control circuit for controlling the discharge circuit.

Abstract: A nonvolatile semiconductor storage device, comprising: a plurality of memory blocks, and at least one high voltage generation circuit, wherein the high voltage generation circuit is formed by a plurality of stages of basic pump cells, each basic pump cell including, a voltage increasing capacitor, an equalizing transistor connected to a voltage of a previous basic pump cell stage, a capacitor for increasing a voltage at a gate of the equalizing transistor, and a transistor which connects the voltage of the previous basic pump cell stage to the gate of the equalizing transistor, the nonvolatile semiconductor storage device further comprises, a discharge circuit connected to a node in the high-voltage generation circuit which has a high voltage, for discharging the node to a potential equal to or lower than a power supply voltage when the high-voltage generation circuit is stopped, and a control circuit for controlling the discharge circuit.

Abstract: A nonvolatile semiconductor memory device of the present invention includes: a plurality of memory blocks each including a memory array including a plurality of memory cells, a plurality of word lines and bit lines provided so as to cross each other for selecting the memory cell, a row decoder for selecting the word line according to an externally-input row address signal, a column decoder for selecting the bit line according to an externally-input column address signal; and at least one internal voltage generation circuit for applying a voltage required for performing data write/erase operations on the memory array, a plurality of first switch circuits are provided such that each first switch circuit is provided between the at least one internal voltage generation circuit and the row decoder or the column decoder, and a switch selection circuit is provided for selectively operating the plurality of first switch circuits.

Abstract: A semiconductor memory device includes a plurality of memory arrays including a plurality of memory cells; a plurality of fuses having one of a disconnected state and a connected state for classifying the plurality of memory arrays into a plurality of banks; and a selection circuit for selecting one of the plurality of banks based on the state of the plurality of the fuses and an address signal.