Abstract: A data processing unit with a TLB purge function has an address counter in which TLB purge data including an address space identifier, segment number, and page number are held. In TLB purge processing, A TLB is indexed by the upper data from the counter so that for the contents of the corresponding entry, an upper address space identifier, an upper segment number, an upper page number, and a valid flag are connected to a TLB hit detector. The lower data from the counter and three mask bits of a nano-instruction are also connected to the TLB hit detector. The TLB hit detector includes three comparators which compare the upper address space identifiers, the upper segment numbers, and the upper page numbers, which are respectively derived from the counter and the TLB. The result of each comparison and a mask bit are ORed. The ORed signal and the valid flag are supplied to an AND gate, thereby checking whether the TLB hit is present or not.

Abstract: In a TLB control system of the invention, each TLB entry has a bit V' representing validity of the entry, a bit VN.sub.i (i=1, . . . , n; n is an integer of 1 or more) representing the validity of TLB entry corresponding to the next page, and address translation data. A first detecting means detects, for each memory access, if correct address translation data is stored in the entry, and if correct address translation data is stored in the TLB entry corresponding to the next page, in accordance with an object virtual address and predetermined fields of the bits V' and VN.sub.i, and the address translation data corresponding to the object virtual address. A second detecting means detects if a single memory access involves a page boundary. A replacing means replaces a corresponding entry of the TLB in accordance with detection results of the first and second detecting means. When the TLB entry is replaced by the replacing means, the bit V' of a replace object TLB entry is set unconditionally. The bit VN.sub.

Abstract: A bit sliced decimal adding/subtracting unit includes an 8-digit decimal adder/subtracter and an offset data generator. In the 8-digit decimal adder/subtracter, eight 1-digit decimal adder/subtracters are intercoupled so as to allow a carry to propagate from the lower order digit to the higher order digit. The offset data generator has first and second logical gates. The first logical gate detects whether or not an addition mode is specified by operation mode data. The second logical gate determines that a signal ZONE representing the format of the data to be operated represents a zone format, and that the addition mode is detected by said first logical gate. The output signal from the first logical gate is used for the first and second bits of the first 4-bit offset data. The output signal from the second logical gate is used for the 0th bit (MSB) and the third bit (LSB) of the first offset data.

Abstract: A data transfer control system which is provided between a main memory for storing programs, data and channel control blocks (CCB's) and I/O processors for controlling channels, for converting an address from the I/O processors to an address specifying the main memory, first address memory which is addressed by combination data of a first identification number identifying the I/O processors and a second identification number identifying the channel and stores a CCB start address of the main memory; second address memory which is addressed by the combination data and stores a start address in a data transfer section included in the channel control block; and a data controller in which, when the first and second identification numbers, a flag, and a relative address are received from the channels through the I/O processors, one of the first and second address memories is selected in accordance with the flag value, the data controller generating an address by adding the address read out from the selected memory

Abstract: The invention provides a data processing unit of a microprogram control system which transfers variable length data from one memory area to another memory area of a main memory.

Abstract: An information processing apparatus for a virtual storage control system performs accessing of a buffer memory from a CPU with sum data of space identification data for identifying multi-virtual spaces and a virtual address within one virtual space. The sum data is also supplied to an address conversion section to perform conversion of the virtual address into a real address in parallel with accessing the buffer memory. If the corresponding record is hit in the buffer memory, the corresponding data is fetched from the buffer memory. If not, data is fetched from a main memory.