Abstract: A memory controlling apparatus retains time information prepared based on performance of a memory and a processor, and determines timing of signal exchange between the memory and the processor based on the time information. An access time to the memory is reduced while maintaining a flexibility to a change of the access time due to increase of memory capacity or reconfiguration of the memory.

Abstract: A pulse train producing apparatus is arranged such that a plurality of first pulse trains are produced correspondingly to a plurality of second pulse trains to be produced so that the leading or trailing edges of the pulses of each first train are adjusted in phase according to the intended phases of corresponding edges of the pulses of a corresponding one of the second pulse trains and the pulses of each first train overlap at their leading or trailing edge portions with the trailing or leading edge portions of a different one of the first trains and two of the first pulse trains having the overlapping portions are applied for cutting away the overlapping portions of the pulses of one of the two pulse trains.