Abstract: In a system including a single main storage or memory and two or more processing units sharing the main storage or memory, there are provided two address arrays for storing the addresses of the data of the main storage or memory which is stored in a buffer storage or memory, one address array storing the same addresses as those stored in the other address array. One of the address arrays is used for reference to the buffer storage or memory by the own or associated processing unit, while its other address array is used for detecting that the store address from another processing unit to the main storage or memory is coincident with one of the addresses stored therein. When the coincidence of addresses is detected, the corresponding address in the other address array is invalidated or cancelled, and the roles of the two address arrays are interchanged. Subsequently, the corresponding address in the one address array is invalidated cancelled.