Abstract: In an output buffer apparatus including a main-buffer circuit including a plurality of first transistors each connected between a first power supply terminal and an output terminal and a plurality of second transistors each connected between a second power supply terminal and the output terminal, and a pre-buffer circuit including a plurality of first pre-drivers each driving one of the first transistors in accordance with a data signal and a plurality of second pre-drivers each driving one of the second transistors in accordance with the data signal, a plurality of first sequential circuits are provided for receiving first impedance adjusting signals in synchronization with the data signal to turn ON the first pre-drivers, and a plurality of second sequential circuits are provided for receiving second impedance adjusting signals in synchronization with the data signal to turn ON the second pre-drivers.

Abstract: An output buffer circuit is disclosed that can enhance AC performance and suppress reflected noise. An output buffer circuit can include a first driver circuit (21) and at least one second driver circuit (2n) for sending signals on a transmission line. A first driver circuit (21) can have an output impedance that essentially matches a characteristic impedance of the transmission line. A signal judging circuit (1) can determine when an input data signal (DATA) makes a transition. During such transition times, a signal may be driven on the transmission line by both the first and second driver circuits (21 to 2n) according to the input data signal. When the input signal data has the same value for a predetermined amount of time, a signal may be driven on the transmission line by the first driver circuit (21), and not the second driver circuit (2n) according to the input data signal. Transitions in an input data signal may be represented by data signals of a signal judging circuit (1) having different values.

Abstract: In an output buffer apparatus including a main-buffer circuit including a plurality of first transistors each connected between a first power supply terminal and an output terminal and a plurality of second transistors each connected between a second power supply terminal and the output terminal, and a pre-buffer circuit including a plurality of first pre-drivers each driving one of the first transistors in accordance with a data signal and a plurality of second pre-drivers each driving one of the second transistors in accordance with the data signal, a plurality of first sequential circuits are provided for receiving first impedance adjusting signals in synchronization with the data signal to turn ON the first pre-drivers, and a plurality of second sequential circuits are provided for receiving second impedance adjusting signals in synchronization with the data signal to turn ON the second pre-drivers.

Abstract: An output buffer circuit is disclosed that can enhance AC performance and suppress reflected noise. An output buffer circuit can include a first driver circuit (21) and at least one second driver circuit (2n) for sending signals on a transmission line. A first driver circuit (21) can have an output impedance that essentially matches a characteristic impedance of the transmission line. A signal judging circuit (1) can determine when an input data signal (DATA) makes a transition. During such transition times, a signal may be driven on the transmission line by both the first and second driver circuits (21 to 2n) according to the input data signal. When the input signal data has the same value for a predetermined amount of time, a signal may be driven on the transmission line by the first driver circuit (21), and not the second driver circuit (2n) according to the input data signal. Transitions in an input data signal may be represented by data signals of a signal judging circuit (1) having different values.