Abstract: A laminated core includes a plurality of electrical steel sheets stacked in a thickness direction, each of the electrical steel sheets includes an annular core back part; a plurality of fastening parts are provided in the core back part at intervals in a circumferential direction; an adhesion region is formed on an outer circumferential side from the fastening parts in the core back part; and a non-adhesion region is formed on an inner circumferential side from the fastening parts in the core back part.

Abstract: A laminated core includes: a plurality of electrical steel sheets stacked in a thickness direction, wherein the electrical steel sheet includes an annular core back part and a plurality of tooth parts protruding from the core back part toward a radial direction and arranged at intervals in a circumferential direction of the core back part, and wherein among the plurality of electrical steel sheets, the tooth parts of the electrical steel sheets located at one side on the outside in a stacking direction are adhered to each other by an adhesion part provided between the tooth parts adjacent to each other in the stacking direction, the tooth parts of the electrical steel sheets located at the other side on the outside in the stacking direction are adhered to each other by an adhesion part provided between the tooth parts adjacent to each other in the stacking direction, and the tooth parts of the electrical steel sheets located at a center part in the stacking direction are not adhered to each other.

Abstract: A laminated core includes a plurality of electrical steel sheets stacked on each other and coated with an insulation coating on both surfaces thereof, and an adhesion part provided between the electrical steel sheets adjacent to each other in a stacking direction and configured to adhere the electrical steel sheets to each other, wherein an adhesion area ratio of the electrical steel sheet by the adhesion part is 1% or more and 40% or less.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial-parallel conversion circuits subjecting received, packetized data to serial-parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial-parallel conversion circuits subjecting received, packetized data to serial-parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: A semiconductor memory device uses in a test mode a clock signal from a tester to allow a test clock conversion circuit and a DLL circuit to generate a rapid internal clock. The internal clock is applied to serial parallel conversion circuits subjecting received, packetized data to serial parallel conversion, and an interface circuit receiving and decoding outputs from the serial-parallel conversion circuits and outputting a command such as ACT to a DRAM core. Furthermore, an internal packet generation circuit uses the internal clock to rapidly generate a testing packet signal. Thus the device's operation can be checked with a low speed tester, without externally receiving a rapid packet signal.

Abstract: This substrate voltage generating circuit (internal voltage generating circuit) includes an oscillator, a p channel transistor, an AND circuit, and a pump circuit. The substrate voltage generating circuit is stopped by applying stop signals S and S to the p channel transistor and the AND circuit connected to the oscillator, and by cutting supply of power supply voltage to the oscillator and a path of output of the oscillator. In order to find current consumption at stand-by of a semiconductor memory device, current consumptions of the whole semiconductor memory device at stand-by before and after operation of the substrate voltage generating circuit is stopped as described above are measured, and the difference between them is calculated. Current consumption of the substrate voltage generating circuit is thus found.

Abstract: A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

Abstract: When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory cell array of a block selected by an operation block selecting circuit through a row decoder and a driving circuit, reads out data written in a normal mode, and determines a memory cell having a threshold value lower than that of a design value upon determination of match of read data and written data.

Abstract: A semiconductor memory device comprises a dynamic memory cell array, a static memory cell array, a plurality of word lines, a plurality of DRAM bit line pairs and a plurality of SRAM bit line pairs. The dynamic memory cell array comprises a plurality of dynamic memory cells arranged in the shape of a matrix. The static memory cell array is arranged adjacent to the dynamic memory cell array. The static memory cell array includes the static memory cells arranged in the shape of a matrix. A plurality of word lines are arranged in a plurality of rows. Each word line is connected to the dynamic and static memory cells arranged in the corresponding rows. A plurality of DRAM bit line pairs are arranged in a plurality of columns. Each DRAM bit line pair is connected to the dynamic memory cells. A plurality of SRAM bit line pairs are arranged in the other plurality of columns. Each SRAM bit line pair is connected to the static memory cells arranged in the corresponding columns.

Abstract: When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory cell array of a block selected by an operation block selecting circuit through a row decoder and a driving circuit, reads out data written in a normal mode, and determines a memory cell having a threshold value lower than that of a design value upon determination of match of read data and written data.

Abstract: When a disturb refresh mode is detected by a mode detecting circuit, a row decoder control circuit simultaneously activates every several word lines of a memory cell array of a block selected by an operation block selecting circuit through a row decoder and a driving circuit, reads out data written in a normal mode, and determines a memory cell having a threshold value lower than that of a design value upon determination of match of read data and written data.

Abstract: In a semiconductor memory device having a spare memory cell array and a spare column decoder and a spare row decoder as redundant circuits, redundancy detecting circuits for testing to see whether the redundant circuits are used or not after completion of the semiconductor memory device as a product are set so as to be capable of providing particular current signals or voltage signals, which indicate that the redundant circuits are used to predetermined external terminals, in response to an output signal at a predetermined logic level from a spare row decoder activating circuit or a spare column decoder activating circuit.

Abstract: A semiconductor memory device having a redundant circuit for electrically replacing a defective memory cell column with a spare memory cell column. An electric fuse (25) is connected between a precharging voltage line (V.sub.BL) and bit lines (BL, BL). When a defective memory cell exists, the precharging voltage tries to vary through this fuse. However, this fuse is cut off, so that the precharging voltage is prevented from varying. Accordingly, data stored in the remaining memory cells are read out correctly and without delay.

Abstract: An address buffer circuit comprises a flip-flop circuit having first and second input nodes and connected between a power-supply potential and a ground potential. In addition, first, second and third transistors are connected in series in that order from the side of the ground between the first input node and the ground potential, to constitute a first input circuit, and fourth, fifth and sixth transistors are connected in series in that order from the side of the ground between the second input node and the ground potential, to constitute a second input circuit. An external address signal is applied to a control terminal of the first transistor, and a reference potential is applied to a control terminal of the fourth transistor. At the time of operating the address buffer circuit, the second and fifth transistors are first turned on, to bring the first and second input circuits into the operating state and then, to bring the flip-flop circuit into the operating state.

Abstract: A dynamic random access memory, which includes a data input buffer, a data input latch circuit, a data output buffer, and a switching circuit. For example, in an operation in a read-write cycle, at first, a data signal to be written is stored in the latch circuit 7 concurrent with inputting of an address signal in response to a signal WE. A data signal read from a memory cell is output via the output buffer in response to a signal OE. The switching circuit is turned on, and the data signal which has been latched is provided to the memory cell via a pair of I/O lines. As a result, the time required for the operation in the read-write cycle is shortened.

Abstract: In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.

Abstract: A semiconductor memory device includes a plurality of operation mode control circuits provided on a memory chip of the device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuits provided on the memory chip, each of the operation mode selection circuits having a fuse element and a bonding pad for selecting one of the plurality of the operation mode control circuits when the fuse element is cut off or the bonding pad is selectively wired, so that various functions can be selectively effected on the same chip.

Abstract: A semiconductor device formed on a semiconductor chip (1) comprises a plurality of first bonding pads (3a, 3d) for receiving an identical external signal, an internal circuit (8) connected to any one of the plurality of the first bonding pads, a second bonding pad (11) for receiving a control signal from outside the semiconductor chip, and a bonding pad selection switch (19) for selecting a bonding pad out of the plurality of first bonding pads and connecting it to the internal circuit in response to the control signal supplied thereto through the second bonding pad.