Patents by Inventor Kazutoshi Ishii
Kazutoshi Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6492692Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.Type: GrantFiled: September 28, 1999Date of Patent: December 10, 2002Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara
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Publication number: 20020153576Abstract: A semiconductor device is provided in which each of contacts between a source and a drain of a MOS transistor and a metallic wiring is either a contact having an arbitrary one side longer than the other side, or source contacts and well contacts are made batting contacts each having an arbitrary one side of a diffusion region having the same polarity as that of a well shorter than the other side. Thus, the contact shape is longitudinal in a transistor width direction, which makes it possible that a large current is caused to flow with a small interval of gates thereof.Type: ApplicationFiled: April 8, 2002Publication date: October 24, 2002Inventors: Toshihiko Omi, Kazutoshi Ishii
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Publication number: 20020084492Abstract: In a power management semiconductor device or analog semiconductor device having a CMOS and a resistor, a conductivity type of a gate electrode of the CMOS is P-type as to both an NMOS and a PMOS, a short channel and a low threshold voltage are possible since an E-type PMOS is surface channel type, the short channel and the low threshold voltage are possible since a buried channel type NMOS is extremely shallow for the reason that arsenic having a small diffusion coefficient can be used as an impurity for threshold control, and the resistor used in a voltage dividing circuit or CR circuit is formed of polycrystalline silicon thinner than the polycrystalline silicon of the same layer as the gate electrode or a thin film metal.Type: ApplicationFiled: August 31, 2001Publication date: July 4, 2002Inventors: Jun Osanai, Hisashi Hasegawa, Sumio Koiwa, Kazutoshi Ishii
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Publication number: 20020068406Abstract: Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.Type: ApplicationFiled: November 30, 2001Publication date: June 6, 2002Inventor: Kazutoshi Ishii
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Publication number: 20020063290Abstract: There is provided a semiconductor integrated circuit device with high electrostatic resistance. A semiconductor device is provided with a transistor for input-output protection having a desired size in which its channel length is varied with respect to a channel width direction.Type: ApplicationFiled: October 31, 2001Publication date: May 30, 2002Inventors: Kazutoshi Ishii, Toshihiko Omi
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Patent number: 6359639Abstract: A thermal head driving integrated circuit capable of preventing the lowering of data transfer speed, and in which the number of bonding pads can be reduced as well as current consumption has a driver circuit in which at least two shift registers are series-arranged in front and rear stages to sequentially transfer print data in a serial signal manner to be read out in a batch mode to drive a plurality of heating resistive elements. A switch circuit is interposed between an output terminal of the front-staged shift register and an input terminal of the rear-staged shift register to selectively connect and disconnect the two shift registers.Type: GrantFiled: October 28, 1999Date of Patent: March 19, 2002Assignee: Seiko Instruments Inc.Inventors: Tatsuya Kitta, Yoshihide Kanakubo, Yasuhiro Moya, Kazutoshi Ishii, Sumitaka Gotou
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Patent number: 6346960Abstract: A thermal head driving integrated circuit may be used to perform an “n” color or “n” gradation printing operation with a simplified circuit having a reduced size by employing a single delay element connected to a plurality of resistive heating elements. The integrated circuit has a plurality of drive units each for driving a respective one of the heating elements and each having a drive transistor for driving a respective heating element, one or more delay elements, the number of delay elements being less than “n”, for supplying delayed print data to the drive transistor, a print data storing unit for storing the print data of each of the “n” types, and a print data supplying unit for supplying print data stored in the print data storing unit to the “n” delay elements.Type: GrantFiled: September 23, 1999Date of Patent: February 12, 2002Assignee: Seiko Instruments Inc.Inventors: Yoshihide Kanakubo, Yasuhiro Moya, Tatsuya Kitta, Kazutoshi Ishii, Sumitaka Goto
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Publication number: 20010038129Abstract: There is provided a MOS transistor in which a leak current is suppressed. Impurity regions which have a polarity different from that to drain regions and a higher concentration than that of a well region in the MOS transistor are formed in lower portions of the drain regions in the MOS transistor, so that extension of depletion layers between the drain regions and the well region to a well region side can be suppressed. In particular, since the extension of the depletion layers to the well region side in the lower portions of the drain regions can be suppressed, a large effect is obtained with respect to a suppression of a current flowing through deeper regions than channel regions.Type: ApplicationFiled: April 11, 2001Publication date: November 8, 2001Inventors: Toshihiko Omi, Kazutoshi Ishii
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Publication number: 20010009288Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.Type: ApplicationFiled: March 9, 2001Publication date: July 26, 2001Applicant: Seiko Instruments Inc.Inventors: Yoshikazu Kojima, Kazutoshi Ishii, Masaaki Kamiya, Yasuhiro Moya
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Patent number: 6222235Abstract: A semiconductor device including multiple high-voltage drive transistors in its output section is improved in electrostatic withstand voltage by connecting electrostatic protection transistors in parallel with the high-voltage drive transistors connected to the output pads. The drain withstand voltage of the electrostatic protection transistors is made lower than the drain withstand voltage of the high-voltage drive transistors. In addition, the channel length of electrostatic protection transistors is made short to enable efficient bipolar operation of the electrostatic protection transistors.Type: GrantFiled: July 10, 1996Date of Patent: April 24, 2001Assignee: Seiko Instruments Inc.Inventors: Yoshikazu Kojima, Kazutoshi Ishii, Masaaki Kamiya, Yasuhiro Moya
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Patent number: 6134136Abstract: Reducing the chip area while improving the manufacturing efficiency as well as reducing costs in a semiconductor integrated circuit device such as a thermal head driver IC. A plurality of terminal electrodes were provided within an external data input/output circuit with an input terminal and output terminal being electrically connected to each other. In addition, an input/output protection circuit was provided to a respective one of such plurality of terminal electrodes with the input terminal and output terminal electrically connected together.Type: GrantFiled: January 26, 1999Date of Patent: October 17, 2000Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Sumitaka Gotou, Yasuhiro Moya, Yoshihide Kanakubo, Tatuya Kitta
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Patent number: 6107128Abstract: Since a field effect MOS transistor can be formed with a reduced number of manufacturing processes, a semiconductor integrated circuit device can be materialized at a low cost. A semiconductor device has a structure in which a gate electrode is provided in the vicinity of the surface of a semiconductor substrate through a gate insulating film, a second conductive type heavily doped impurity region is provided in a region adjacent to a part of the gate electrode through a part of the gate insulating film and a part of a thick oxide film, another second conductive type heavily doped impurity region is provided in a region adjacent to an opposite part of the gate electrode opposing the part of the gate electrode through the part of the gate insulating film and a part of another thick oxide film, and a first conductive type heavily doped impurity region for device isolation is provided so as to surround the gate electrode and the second conductive type heavily doped impurity regions.Type: GrantFiled: June 2, 1999Date of Patent: August 22, 2000Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Sumitaka Gotou, Yasuhiro Moya, Tatsuya Kitta, Yoshihide Kanakubo
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Patent number: 6022792Abstract: To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.Type: GrantFiled: March 12, 1997Date of Patent: February 8, 2000Assignee: Seiko Instruments, Inc.Inventors: Kazutoshi Ishii, Naoto Inoue, Koushi Maemura, Shoji Nakanishi, Yoshikazu Kojima, Kiyoaki Kadoi, Takao Akiba, Yasuhiro Moya, Kentaro Kuhara
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Patent number: 5663589Abstract: A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut.Type: GrantFiled: September 28, 1994Date of Patent: September 2, 1997Assignee: Seiko Instruments Inc.Inventors: Yutaka Saitoh, Jun Osanai, Yoshikazu Kojima, Kazutoshi Ishii
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Patent number: 5449637Abstract: An electroconductive or insulative film 100 is formed over a surface of a semiconductor substrate 1. A first photoresist 101 is coated over the film 100, and is then patterned. The film 100 is selectively removed by etching to expose a given area of the substrate 1. Subsequently an impurity of the first conductivity type is doped into the exposed area to form a first impurity region. After removing the first photoresist 101, a second photoresist 103 is coated entirely over the film 100, and is then patterned. Subsequently, the film 100 is selectively removed from another given area by etching. Another impurity of the second conductivity type is doped into the exposed area to form a second impurity region 104. Only the two steps of the photoresist patterning are carried out to form the impurity regions of the different conductivity types, thereby reducing production cost of the semiconductor device.Type: GrantFiled: September 27, 1993Date of Patent: September 12, 1995Assignee: Seiko Instruments, Inc.Inventors: Yutaka Saito, Yoshikazu Kojima, Kazutoshi Ishii
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Patent number: 5324677Abstract: A semiconductor nonvolatile memory device of the gate insulating type is comprised of a semiconductor substrate, an electrically erasable programmable memory cell having a gate oxide film disposed on the substrate, a floating gate electrode formed on the gate oxide film, and a control gate electrode formed in the substrate under the gate oxide film and separated from the floating gate electrode through the gate oxide film so as to control potential level of the floating gate electrode to effect writing and erasing operation of the memory cell, and a peripheral circuit including a transistor of the gate insulating type having another gate oxide film disposed on the same substrate and formed concurrently with the first mentioned gate oxide film.Type: GrantFiled: December 5, 1990Date of Patent: June 28, 1994Assignee: Seiko Instruments Inc.Inventor: Kazutoshi Ishii
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Patent number: 5065222Abstract: A passivation film of MOS semiconductor device is composed of a first passivation layer and a second passivation layer formed on the first passivation layer. The first passivation layer comprises silicon dioxide containing phosphorus in 0.5 percent or less and having a film thickness of 1500 .ANG. or more. The second passivation layer comprises silicon oxynitride or silicon nitride.Type: GrantFiled: November 9, 1988Date of Patent: November 12, 1991Assignee: Seiko Instruments Inc.Inventor: Kazutoshi Ishii
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Patent number: D368521Type: GrantFiled: April 28, 1994Date of Patent: April 2, 1996Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiko Asai, Satoru Kotani, Kazutoshi Ishii, Masayuki Yoshii, Koji Kubo