Patents by Inventor Kazutoshi Nagasawa

Kazutoshi Nagasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190270043
    Abstract: A trap device includes a first gas inlet introducing a waste gas after use, a heater-installed duct provided with a heater in a first gas flow path through which the introduced waste gas flows, a trap capturing by-products by cooling the waste gas after flowing through the heater-installed duct, and a communication member connecting the heater-installed duct to the trap.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 5, 2019
    Inventor: Kazutoshi NAGASAWA
  • Patent number: 4376657
    Abstract: In a gettering method for processing semiconductor wafers a semiconductor wafer such as a silicon wafer is first annealed in a non-oxidizing atmosphere, for example, in a nitrogen atmosphere, at a temperature in the range of 950.degree. to 1,300.degree. C., preferably at 1,050.degree. C., for more than 10 minutes, for example for four (4) hours, to diffuse out oxygen near the surfaces of the semiconductor wafer. Then the semiconductor wafer is annealed at a temperature in the range of 600.degree. to 800.degree. C., for example at 650.degree. C., for more than one hour, preferably for 16 hours, to create in the interior of the semiconductor wafer microdefects of high density.
    Type: Grant
    Filed: December 5, 1980
    Date of Patent: March 15, 1983
    Assignee: VLSI Technology Research Association
    Inventors: Kazutoshi Nagasawa, Seigo Kishino, Yoshiaki Matsushita, Masaru Kanamori
  • Patent number: 4314595
    Abstract: A silicon single crystal wafer is subjected to two-stage heat treatment. In the first-stage it is heated at a temperature within the range of between 500.degree. C. and 1,000.degree. C. Subsequently the thus heated wafer is heated at a temperature higher than that at the first stage. Thus, a nondefective zone is formed in the surface region of the wafer, and the interior zone of the wafer becomes rich in micro defects capable of gettering impurities such as heavy metals.
    Type: Grant
    Filed: January 8, 1980
    Date of Patent: February 9, 1982
    Assignee: VLSI Technology Research Association
    Inventors: Kazuhiko Yamamoto, Yoshiaki Matsushita, Masaru Kanamori, Kazutoshi Nagasawa, Naotsugu Yoshihiro, Seigo Kishino