Patents by Inventor Kazutoshi Nakajima

Kazutoshi Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7259439
    Abstract: In a semiconductor photodetector 1 according to the present invention, flat surfaces of three steps with different heights are formed in a top surface portion of a semi-insulating GaAs substrate 2. An n-type GaAs layer 3, an i-type GaAs layer 4, and a p-type GaAs layer 5 are successively deposited on the lower step surface formed in a central region of the semi-insulating GaAs substrate 2. Furthermore, a p-side ohmic electrode 6 is provided astride and above a flat surface formed by the p-type GaAs layer 5 and the upper step surface of the semi-insulating GaAs substrate 2, and an n-side ohmic electrode 7 is provided astride and above a flat surface formed by the n-type GaAs layer 3 and the middle step surface of the semi-insulating GaAs substrate 2.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: August 21, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Kazutoshi Nakajima
  • Patent number: 7217932
    Abstract: A UV sensor (1) includes a container (5) in which the upper end opening of a metal side tube (2) is sealed with a front plate (3) composed of borosilicate glass as an incident light window and the lower end opening is sealed with a base plate (4). The front plate (3) serving as an incident light window constitutes part of the wall of container (5) by sealing the upper end opening of the metal side tube (2). A pin-type photodiode (6) is disposed inside the container (5). The pin-type photodiode (6) comprises a photoabsorption layer (9) formed from InxGa(1?x)N (0<x<1) between an n-type contact layer (8) and a p-type contact layer (10).
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: May 15, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Minoru Niigaki, Yasufumi Takagi, Kazutoshi Nakajima, Yoshitaka Suzuki, Nobuharu Suzuki
  • Patent number: 7214971
    Abstract: A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the boundary between the portion of the p-type layer and the middle region. An n-type layer on the p-type layer has a top surface including a portion on a level with the upper region. Another electrode covers at least part of the boundary between the portion of the n-type layer and the upper region.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: May 8, 2007
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Minoru Niigaki, Kazutoshi Nakajima
  • Publication number: 20070096648
    Abstract: A semiconductor photocathode 1 includes: a transparent substrate 11; a first electrode 13, formed on the transparent substrate 11 and enabling passage of light that has been transmitted through the transparent substrate 11; a window layer 14, formed on the first electrode 13 and formed of a semiconductor material with a thickness of no less than 10 nm and no more than 200 nm; a light absorbing layer 15, formed on the window layer 14, formed of a semiconductor material that is lattice matched to the window layer 14, is narrower in energy band gap than the window layer 14, and in which photoelectrons are excited in response to the incidence of light; an electron emission layer 16, formed on the light absorbing layer 15, formed of a semiconductor material that is lattice matched to the light absorbing layer 15, and emitting the photoelectrons excited in the light absorbing layer 15 to the exterior from a surface; and a second electrode 18, formed on the electron emission layer.
    Type: Application
    Filed: October 25, 2006
    Publication date: May 3, 2007
    Inventors: Kazutoshi Nakajima, Minoru Niigaki, Tomoko Mochizuki, Toru Hirohata
  • Patent number: 7094664
    Abstract: Multilayer films (2 to 7 ) containing a light absorption layer (4) are formed on a GaAs substrate. After laminating the GaAs substrate (1) and a glass substrate (8) so that an uppermost surface film (7) of the multilayer film and the glass substrate (8) may come into contact with each other, by pressurizing between the GaAs substrate (1) and the glass substrate (8) and heating them together, both substrates (1) and (8) are fusion-bonded. Next, the GaAs substrate (1) and the buffer layer (2) are first removed, and then the etch stop layer (3) is removed. Then, while coming into contact with the light absorption layer (4), comb-type Schottky electrodes (10) and (11), which are mutually apart, are formed.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: August 22, 2006
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Minoru Niigaki, Kazutoshi Nakajima
  • Publication number: 20050173712
    Abstract: In a semiconductor photodetector 1 according to the present invention, flat surfaces of three steps with different heights are formed in a top surface portion of a semi-insulating GaAs substrate 2. An n-type GaAs layer 3, an i-type GaAs layer 4, and a p-type GaAs layer 5 are successively deposited on the lower step surface formed in a central region of the semi-insulating GaAs substrate 2. Furthermore, a p-side ohmic electrode 6 is provided astride and above a flat surface formed by the p-type GaAs layer 5 and the upper step surface of the semi-insulating GaAs substrate 2, and an n-side ohmic electrode 7 is provided astride and above a flat surface formed by the n-type GaAs layer 3 and the middle step surface of the semi-insulating GaAs substrate 2.
    Type: Application
    Filed: December 26, 2002
    Publication date: August 11, 2005
    Inventor: Kazutoshi Nakajima
  • Publication number: 20050051784
    Abstract: A semiconductor light-receiving device has a substrate including upper, middle and lower regions in its front side. A p-type layer on the lower region has a top surface including a portion on a level with the middle region. An electrode covers at least part of the boundary between the portion of the p-type layer and the middle region. An n-type layer on the p-type layer has a top surface including a portion on a level with the upper region. Another electrode covers at least part of the boundary between the portion of the n-type layer and the upper region.
    Type: Application
    Filed: June 10, 2004
    Publication date: March 10, 2005
    Inventors: Minoru Niigaki, Kazutoshi Nakajima
  • Publication number: 20050014321
    Abstract: Multilayer films 2 to 7 containing a light absorption layer 4 are formed on a GaAs substrate. After laminating the GaAs substrate 1 and a glass substrate 8 so that an uppermost surface film 7 of the multilayer film and the glass substrate 8 may come into contact with each other, by pressurizing between the GaAs substrate 1 and the glass substrate 8 and heating them together, both substrates 1 and 8 are fusion-bonded. Next, the GaAs substrate 1 and the buffer layer 2 are first removed, and then the etch stop layer 3 is removed. Then, while coming into contact with the light absorption layer 4, comb-type Schottky electrodes 10 and 11, which are mutually apart, are formed.
    Type: Application
    Filed: November 9, 2001
    Publication date: January 20, 2005
    Inventors: Minoru Niigaki, Kazutoshi Nakajima
  • Publication number: 20040135094
    Abstract: A UV sensor 1 comprises a container 5 in which the upper end opening of a metal side tube 2 is sealed with a front plate 3 composed of Kovar glass as an incident light window and the lower end opening is sealed with a base plate 4. The front plate 3 serving as an incident light window constitutes part of the wall of container 5 by sealing the upper end opening of the metal side tube 2. A pin-type photodiode 6 is disposed inside the container 5. The pin-type photodiode 6 comprises a photoabsorption layer 9 formed from InxGa(1-x)N (0<x<1) between an n-type contact layer 8 and a p-type contact layer 10.
    Type: Application
    Filed: November 21, 2003
    Publication date: July 15, 2004
    Applicant: Hamamatsu Photonics K.K.
    Inventors: Minoru Niigaki, Yasufumi Takagi, Kazutoshi Nakajima, Yoshitaka Suzuki, Nobuharu Suzuki
  • Patent number: 5109358
    Abstract: An optical flip-flop circuit which includes an electrical power source for providing an electrical signal, a light-receiving element provided in series with the power source for switching the electrical signal in response to an optical signal, a light-emitting element for emitting the optical signal in response to the electric signal, an electrical signal path between the light-receiving element and the light-emitting element, whereby the electrical signal passes from the power source to the light-emitting element in response to the optical signal received by the light-receiving element, a light path for directing the optical signal from the light-emitting element to the light-receiving element, wherein the light path and the electrical signal path form a signal loop through which a signal circulates, said circulating signal comprising the electrical signal through the electrical signal path portion of the signal loop and the optical signal through the light path portion of the signal loop, and input/output m
    Type: Grant
    Filed: October 17, 1989
    Date of Patent: April 28, 1992
    Assignee: Hamamatsu Photonics Kabushiki Kaisha
    Inventors: Yoshihiko Mizushima, Kazutoshi Nakajima, Toru Hirohata, Takashi Iida, Yoshihisa Warashina, Kenichi Sugimoto, Hirofumi Kan
  • Patent number: 5068815
    Abstract: SUM and CARRY output signals of a first optical half adder are provided to one input terminal of a second optical half adder and an optical latch memory, respectively, and an output signal of the optical latch memory is provided to the other input terminal of the second optical half adder. Input and output of the two optical half adders and optical latch memory are performed through an optical signal. Each optical half adder includes two light-receiving elements each having a symmetrical electrode arrangement in which two Schottky junctions are connected to each other opposite in polarity, and peripheral elements of resistors, a capacitor and an amplifier.
    Type: Grant
    Filed: June 21, 1990
    Date of Patent: November 26, 1991
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Yoshihiko Mizushima, Kazutoshi Nakajima, Toru Hirohata, Takashi Iida, Yoshihisa Warashina, Kenichi Sugimoto, Tomoko Suzuki, Hirofumi Kan
  • Patent number: 5051573
    Abstract: A plurality of ultra-high speed light receiving elements are provided each of which has two rectifier junctions being connected to each other opposite in polarity and has a substantially symmetrical electrode arrangement. A bias voltage is applied to each of the light receiving elements from one or a plurality of power sources. Electrical signals produced by the light receiving elements in response to input optical pulse signals are superposed on one another to produce one or a plurality of output electrical signals representing a predetermined logic operation with respect to the input optical pulse signals. Depending on the arrangement of its elements, the optical logic operation system functions as an OR circuit, AND circuit, NOT circuit, EXCLUSIVE OR circuit, or half-adder circuit.
    Type: Grant
    Filed: November 14, 1989
    Date of Patent: September 24, 1991
    Assignee: Hamamatsu Photonics Kabushiki kaisha
    Inventors: Yoshihiko Mizushima, Kazutoshi Nakajima, Toru Hirohata, Takashi Iida, Yoshihisa Warashina, Kenichi Sugimoto, Hirofumi Kan
  • Patent number: 5034921
    Abstract: An optical memory circuit comprises two photodetectors, and an intermediate signal conductor for connecting the two photodetectors, wherein the two photodetectors and the signal conductor are connected in series in a closed circuit, wherein each of the photodetectors comprises two spaced Schottky electrodes symmetrically disposed on a semiconductor substrate and the signal conductor has a capacitance with a time constant of a potential of the signal conductor such that charges are stored in the signal conductor when an optical write signal is incident on one photodetector and stored charges are released from the signal conductor when an optical read signal is incident on the other photodetector.
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: July 23, 1991
    Assignee: Hamamatsu Photonics Kabushiki Kaisha
    Inventors: Kazutoshi Nakajima, Hirofumi Kan, Kenichi Sugimoto, Yoshihiko Mizushima, Toru Hirohata, Takashi Iida, Yoshihisa Warashina, Toru Hirohata, Takashi Iida
  • Patent number: 5020064
    Abstract: An electromagnetic wave device having an amplification function comprises a medium containing free carriers, means for applying a magnetic field to the medium, means for applying an input electromagnetic wave to the medium in a direction perpendicular to the magnetic field, and means for generating an electric field to accelerating the carriers in the direction of the input electromagnetic wave. A frequency of the input electromagnetic wave is within the range of the plasma frequency plus or minus the cyclotron frequency, and a polarization direction of the input electromagnetic wave is perpendicular both to the magnetic field and its own traveling direction. Furthermore, the device has such functions as oscillation, modulation, frequency conversion, etc. depending on the type of added units.
    Type: Grant
    Filed: August 14, 1989
    Date of Patent: May 28, 1991
    Assignee: Hamamatsu Photonics Kabushiki Kaisha
    Inventors: Yoshihiko Mizushima, Takashi Iida, Toru Hirohata, Kenichi Sugimoto, Yoshihisa Warashina, Kazutoshi Nakajima