Patents by Inventor Kazutoshi Ohmori

Kazutoshi Ohmori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110291280
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: August 10, 2011
    Publication date: December 1, 2011
    Inventors: Kazutoshi OHMORI, Tsuyoshi TAMARU, Naohumi OHASHI, Kiyohiko SATO, Hiroyuki MARUYAMA
  • Patent number: 8012871
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: September 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20100210107
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: April 30, 2010
    Publication date: August 19, 2010
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 7723849
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20070105369
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 7176121
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 6812127
    Abstract: An interlayer dielectric film that surrounds via holes for connecting wirings of a second wiring layer and the wirings of third wiring layer is constituted of a dielectric material having a relatively smaller Young's modulus compared with the Young's modulus of a dielectric material constituting a dielectric film that surrounds wiring grooves in dual damascene wirings, which can improve the heat resistance and electromigration resistance of the dual damascene wirings.
    Type: Grant
    Filed: November 16, 2001
    Date of Patent: November 2, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Oshima, Hiroshi Miyazaki, Hideo Aoki, Kazutoshi Ohmori
  • Publication number: 20040192032
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: October 15, 2003
    Publication date: September 30, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20040152336
    Abstract: Disclosed here is a method for manufacturing a semiconductor device, which can prevent films from delamination and improve the reliability of the semiconductor. A first insulating film comprising a silicon carbide film, silicon carbide nitride film, or silicon oxide nitride film is formed as a barrier insulating film of the wiring, and then a second insulating film comprising a fluorine containing silicon oxide film is formed on the first insulating film by a high density plasma CVD method as a low permittivity insulating film. And, when forming the second insulating film, the semiconductor substrate is heated up to a predetermined deposition temperature using a heat-up plasma generated by a gas containing no oxygen such as an argon plasma. When the substrate reaches the predetermined deposition temperature, the insulating film deposition gas is introduced into the deposition chamber to deposit the second insulating film on the first insulating film.
    Type: Application
    Filed: January 7, 2004
    Publication date: August 5, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Noriko Miura, Kazutoshi Ohmori, Kiyohiko Sato, Junji Noguchi, Tsuyoshi Tamaru
  • Patent number: 6767782
    Abstract: Charge-up damages to a substrate are reduced in a manufacturing process using plasma, and the reliability of a semiconductor device is improved. By forming an insulating film on the back of a substrate before a step of forming a first wiring layer, even if a plasma CVD method, a sputtering method, or a dry-etching method is used in a wiring-forming step executed later, then it is possible to suppress electric charges which are generated on the substrate and which flow to the ground potential through the substrate, and to prevent damages to the substrate due to charge-up.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: July 27, 2004
    Assignees: Renesas Technology Corp., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Takeshi Saikawa, Ryohei Maeno, Sadayuki Okudaira, Tetsuo Saito, Tsuyoshi Tamaru, Kazutoshi Ohmori
  • Publication number: 20020168827
    Abstract: Charge-up damages to a substrate are reduced in a manufacturing process using plasma, and the reliability of a semiconductor device is improved.
    Type: Application
    Filed: February 26, 2002
    Publication date: November 14, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takeshi Saikawa, Ryohei Maeno, Sadayuki Okudaira, Tetsuo Saito, Tsuyoshi Tamaru, Kazutoshi Ohmori
  • Publication number: 20020100984
    Abstract: An interlayer dielectric film that surrounds via holes for connecting wirings of a second wiring layer and the wirings of a third wiring layer is constituted of a dielectric material having a relatively smaller Young's modulus compared with the Young's modulus of a dielectric material constituting a dielectric film that surrounds wiring grooves in dual damascene wirings, which can improve the heat resistance and electromigration resistance of the dual damascene wirings.
    Type: Application
    Filed: November 16, 2001
    Publication date: August 1, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki Oshima, Hiroshi Miyazaki, Hideo Aoki, Kazutoshi Ohmori