Patents by Inventor Kazutoshi Oomori
Kazutoshi Oomori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7282434Abstract: A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.Type: GrantFiled: July 14, 2006Date of Patent: October 16, 2007Assignee: Renesas Technology Corp.Inventors: Tsuyoshi Tamaru, Kazutoshi Oomori, Noriko Miura, Hideo Aoki, Takayuki Oshima
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Publication number: 20060258149Abstract: A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.Type: ApplicationFiled: July 14, 2006Publication date: November 16, 2006Inventors: Tsuyoshi Tamaru, Kazutoshi Oomori, Noriko Miura, Hideo Aoki, Takayuki Oshima
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Patent number: 7084055Abstract: It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750° C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes.Type: GrantFiled: September 1, 2004Date of Patent: August 1, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Tsuyoshi Fujiwara, Katsuyuki Asaka, Yasuhiro Nariyoshi, Yoshinori Hoshino, Kazutoshi Oomori
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Patent number: 7078815Abstract: A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.Type: GrantFiled: February 14, 2005Date of Patent: July 18, 2006Assignee: Hitachi, Ltd.Inventors: Tsuyoshi Tamaru, Kazutoshi Oomori, Noriko Miura, Hideo Aoki, Takayuki Oshima
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Publication number: 20050151262Abstract: A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.Type: ApplicationFiled: February 14, 2005Publication date: July 14, 2005Inventors: Tsuyoshi Tamaru, Kazutoshi Oomori, Noriko Miura, Hideo Aoki, Takayuki Oshima
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Patent number: 6856019Abstract: A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.Type: GrantFiled: August 9, 2002Date of Patent: February 15, 2005Assignee: Renesas Technology Corp.Inventors: Tsuyoshi Tamaru, Kazutoshi Oomori, Noriko Miura, Hideo Aoki, Takayuki Oshima
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Publication number: 20050026358Abstract: It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, a high density plasma silicon oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor, to be connected to the other of the source and drain region of the memory cell selection MISFET, is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.Type: ApplicationFiled: September 1, 2004Publication date: February 3, 2005Inventors: Tsuyoshi Fujiwara, Katsuyuki Asaka, Yasuhiro Nariyoshi, Yoshinori Hoshino, Kazutoshi Oomori
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Patent number: 6803271Abstract: It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.Type: GrantFiled: July 2, 2002Date of Patent: October 12, 2004Assignees: Renesas Technology Corp., Hitachi Tohbu Semiconductor, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Tsuyoshi Fujiwara, Katsuyuki Asaka, Yasuhiro Nariyoshi, Yoshinori Hoshino, Kazutoshi Oomori
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Publication number: 20030030146Abstract: A semiconductor integrated circuit device comprises a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film so that free F generated in the SiOF film is trapped with the silicon oxynitride film.Type: ApplicationFiled: August 9, 2002Publication date: February 13, 2003Inventors: Tsuyoshi Tamaru, Kazutoshi Oomori, Noriko Miura, Hideo Aoki, Takayuki Oshima
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Publication number: 20030032233Abstract: The invention is provided to prevent breakage and separation of wiring of a semiconductor integrated circuit device such as a bit-line of a DRAM. An HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of high density plasma CVD technique, and subjected to RTA (heat treatment) at 750° C. The surface is polished, and then a capacitor to be connected to other source and drain region of the memory cell selection MISFET is formed. As the result, even when a tantalum oxide film that is an capacitance insulating film of the capacitor is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.Type: ApplicationFiled: July 2, 2002Publication date: February 13, 2003Inventors: Tsuyoshi Fujiwara, Katsuyuki Asaka, Yasuhiro Nariyoshi, Yoshinori Hoshino, Kazutoshi Oomori