Abstract: Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals IN1 to IN3 are supplied to diffusion layer regions 221, 223 and 225 via transistors 301 to 303, and are accumulated as electric charge. A clock signal is applied to signal lines 121 and 122 alternately connected to gate electrodes 211 to 216, thus allowing the accumulated electric charge to be transferred to the right direction. Electric charge/voltage conversion amplifiers 411 to 413 are connected to the diffusion layer regions 221, 223 and 225, and the accumulated electric charge is converted into voltage and is output to output terminals VOUT1 to VOUT3 as analog signals. A scan-in terminal Sin is connected to a diffusion layer region 220, and a scan-out terminal Sout is connected to the diffusion layer region 225 via an electric charge/voltage conversion amplifier 401.

Abstract: A semiconductor memory device provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.

Abstract: Observability and controllability in a test of an analog LSI are increased. Analog signals input from input terminals IN1 to IN3 are supplied to diffusion layer regions 221, 223 and 225 via transistors 301 to 303, and are accumulated as electric charge. A clock signal is applied to signal lines 121 and 122 alternately connected to gate electrodes 211 to 216, thus allowing the accumulated electric charge to be transferred to the right direction. Electric charge/voltage conversion amplifiers 411 to 413 are connected to the diffusion layer regions 221, 223 and 225, and the accumulated electric charge is converted into voltage and is output to output terminals VOUT1 to VOUT3 as analog signals. A scan-in terminal Sin is connected to a diffusion layer region 220, and a scan-out terminal Sout is connected to the diffusion layer region 225 via an electric charge/voltage conversion amplifier 401.

Abstract: Disclosed herein is a liquid crystal display apparatus, including, a pixel array section, a first data line, a second data line, a writing unit, a voltage supply control unit, a data line short-circuiting unit, a reading out unit, and a testing unit.

Abstract: The present invention provides a semiconductor device, including: a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip through a plurality of bumps having not only a number of main bumps necessary for operation between the chips but also a predetermined number of measurement and control input bumps. Each of the first and second chips includes a plurality of measurement path switches individually connected to the main bumps, a plurality of current path switches connected to connecting points between the main bumps and the measurement path switches, and a control circuit for the measurement path switches, the first semiconductor chip further including a plurality of measurement and control terminals for inputting a control signal of the control circuit and supplying fixed current to be supplied to the current path switches and then measuring the voltage at the connecting points.

Abstract: A defective pixel examination method includes the steps of applying different voltages to a capacitive element of a first pixel section and a capacitive element of a second pixel section among the plurality of pixel sections; turning on a switch provided between an input electrode of a pixel transistor in the first pixel section and an input electrode of a pixel transistor in the second pixel section and short-circuiting the input electrode of the first pixel transistor and the input electrode of the second pixel transistor; reading a voltage of the capacitive element of the first pixel section and a voltage of the capacitive element of the second pixel section; and detecting defects of a pixel section on the basis of the result of the comparison between the voltage of the capacitive element of the first pixel section and the voltage of the capacitive element of the second pixel section.

Abstract: The disclosed semiconductor memory device exhibits improved error correction capability shorter read/write times, and removes or reduces the need for redundant memory The semiconductor device has a data input portion for receiving one page of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words, and transferring the main code words to one of a plurality of memory banks. The semiconductor device also includes a data output portion for receiving one page worth of data, including main code words transferred from the data latch circuit, correcting errors in the data when the data includes fewer than a predetermined number of errors for each main code word, adding the error information to each read code word, and outputting the result.

Abstract: A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and/or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.

Abstract: The present invention provides a semiconductor device, including: a first semiconductor chip, and a second semiconductor chip connected to the first semiconductor chip through a plurality of bumps having not only a number of main bumps necessary for operation between the chips but also a predetermined number of measurement and control input bumps. Each of the first and second chips includes a plurality of measurement path switches individually connected to the main bumps, a plurality of current path switches connected to connecting points between the main bumps and the measurement path switches, and a control circuit for the measurement path switches, the first semiconductor chip further including a plurality of measurement and control terminals for inputting a control signal of the control circuit and supplying fixed current to be supplied to the current path switches and then measuring the voltage at the connecting points.

Abstract: Disclosed herein is a liquid crystal display apparatus, including, a pixel array section, a first data line, a second data line, a writing unit, a voltage supply control unit, a data line short-circuiting unit, a reading out unit, and a testing unit.

Abstract: A defective pixel examination method includes the steps of applying different voltages to a capacitive element of a first pixel section and a capacitive element of a second pixel section among the plurality of pixel sections; turning on a switch provided between an input electrode of a pixel transistor in the first pixel section and an input electrode of a pixel transistor in the second pixel section and short-circuiting the input electrode of the first pixel transistor and the input electrode of the second pixel transistor; reading a voltage of the capacitive element of the first pixel section and a voltage of the capacitive element of the second pixel section; and detecting defects of a pixel section on the basis of the result of the comparison between the voltage of the capacitive element of the first pixel section and the voltage of the capacitive element of the second pixel section.

Abstract: A semiconductor integrated circuit including an input terminal and an input circuit connected to the input terminal includes the following elements. A testing circuit is provided between the input terminal and the input circuit, and changes a resistance value between the input terminal and a predetermined potential. A test terminal is adapted to operate the testing circuit.

Abstract: A semiconductor memory device able to strengthen an error correction capability, able to shorten a write time and/or a read time, able to make a redundant memory unnecessary or smaller, and consequently able to achieve a reduction of size and a reduction of cost, provided with a data input portion for receiving 1 page's worth of data, dividing it to a plurality of code words, generating and adding check code (parity data), for each code word, successively forming main code words and transferring the same to a bank (A) or a bank (B), and a data output portion for receiving 1 page's worth of data including main code words transferred from the data latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the error information for read each read code word except check code (parity data), and transferring the same to a host side, and a signal processing system using the same.

Abstract: A semiconductor device includes on the same chip at least an I/O region where an input/output pad is formed and active regions where a circuit can be mounted, where a plurality of logic circuits having the same functions or different functions are mounted in the active regions on the same chip.

Abstract: MOS transistors A and B form a transistor circuit (an inverter in this case). A MOS transistor D is one for interrupting leakage current that has a channel length longer than those of the MOS transistors A and B. Under the action of an enable terminal (Enable), the MOS transistor D conducts only while the circuit is operated, and does not conduct and thereby interrupts leakage current while the circuit is in a standby state. A MOS transistor C does not produce effect while the circuit is operated, and makes the potential of an output terminal (Output) a high potential or a low potential (not intermediate potential) only while the circuit is in the standby state. Therefore, the circuit controls unnecessary through-transistor current of a standby type circuit in a succeeding stage, which current is conventionally caused at an intermediate potential during standby.

Abstract: In a conventional LSI, since a minimum chip size is inevitably determined by the number and size of input/output pads formed on a chip, an no-patterned region occurs in an active region surrounded by an I/O region in a highly integrated circuit or a circuit with a small number of gates. The present invention intends to solve this problem to improve a semiconductor device. In a semiconductor device comprising on the same chip at least an I/O region where an input/output pad is formed and active regions where a circuit can be mounted, a plurality of logic circuits having the same functions or different functions are mounted in the active regions on the same chip.

Abstract: MOS transistors A and B form a transistor circuit (an inverter in this case). A MOS transistor D is one for interrupting leakage current that has a channel length longer than those of the MOS transistors A and B. Under the action of an enable terminal (Enable), the MOS transistor D conducts only while the circuit is operated, and does not conduct and thereby interrupts leakage current while the circuit is in a standby state. A MOS transistor C does not produce effect while the circuit is operated, and makes the potential of an output terminal (Output) a high potential or a low potential (not intermediate potential) only while the circuit is in the standby state. Therefore, the circuit controls unnecessary through-transistor current of a standby type circuit in a succeeding stage, which current is conventionally caused at an intermediate potential during standby.

Abstract: A servo control system for a shock-proof disk player comprising a digital signal processor, a voltage-controlled oscillator, a reference clock generator, a clock mode changeover switch, a phase comparator for controlling a head-rotating spindle motor, and a bulk memory of a large capacity for storage of data, wherein the phase lock of a PLL at the time of a seek is switched on or off under control to thereby shorten the required seek time. The clock signal frequency is selectively changed in such a manner as to lock the PLL in accordance with the rotation rate, whereby the power consumption can be lowered. The bulk memory is used as a data buffer, and the servo system is controlled as the data are read out from the memory while the data quantity stored and left therein is detected, so that a reduction of the power consumption can be achieved with another advantage of enhancing the resistance against shock.

Abstract: An input signal and a signal obtained by delaying that input signal are compared, an output signal is produced based on the amount of the delay, and the output signal is used to form a control signal by a low pass filter etc. The delay of the input signal is controlled so as to produce a plurality of stable clocks and enable stable high speed signal processing without raising the clock frequency.

Abstract: An input signal and a signal obtained by delaying that input signal are compared, an output signal is produced based on the amount of the delay, and the output signal is used to form a control signal by a low pass filter. The delay of the input signal is controlled so as to produce a plurality of stable clocks and enable stable high speed signal processing without raising the clock frequency.