Patents by Inventor Kazutoshi Sugimura

Kazutoshi Sugimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240014298
    Abstract: A diode formed by a polysilicon layer is disposed between a field oxide film and an interlayer insulating film, in a semiconductor substrate, at a front surface of the semiconductor substrate. One resist mask is used to form contact holes of the interlayer insulating film and contact trenches and a p+-type region of the polysilicon layer. The contact trenches are continuously formed from bottoms of the contact holes, respectively, in a depth direction. A low-resistance contact between the p+-type region and an anode electrode is formed at least at a bottom of the contact trench. During the formation of the p+-type region, while a p-type impurity is ion-implanted in an inner wall of the contact trench 3b, an n-type cathode region maintains an n-type conductivity thereof and a contact with a cathode electrode is formed at sidewalls of the contact trench.
    Type: Application
    Filed: May 30, 2023
    Publication date: January 11, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroyuki MIYASHITA, Masayuki MOMOSE, Kazutoshi SUGIMURA, Kenji KOJIMA
  • Patent number: 10388740
    Abstract: The position of the side wall of a metal electrode is precisely controlled and the coverage of a layer above the metal electrode is improved. A semiconductor device is provided, including: a semiconductor substrate; and a metal electrode formed above an upper surface of the semiconductor substrate, wherein a side wall of the metal electrode includes a lower portion contacting the semiconductor substrate, and an upper portion that is formed upper than the lower portion and has a smaller inclination relative to the upper surface of the semiconductor substrate than the lower portion. An active region formed in the semiconductor substrate is further included, and the metal electrode may be a field plate formed on an outer side relative to the active region on the upper surface of the semiconductor substrate. The upper portion of the side wall of the field plate may have an upward-convex shape.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: August 20, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Eri Ogawa, Yuichi Onozawa, Kazutoshi Sugimura, Hiroyuki Tanaka, Kota Ohi, Yoshihiro Ikura
  • Patent number: 10181508
    Abstract: Provided is a guard ring section to which a fine processing is easily applied. Provided is a semiconductor device comprising: a semiconductor substrate; an active region formed in the semiconductor substrate; and a guard ring section formed more outside than the active region in the semiconductor substrate, wherein the guard ring section includes: a guard ring formed in a circular pattern on an upper surface of the semiconductor substrate; an interlayer insulating film formed above the guard ring; a field plate formed in a circular pattern along the guard ring and above the interlayer insulating film; and a tungsten plug formed in a circular pattern along the guard ring and penetrating the interlayer insulating film to connect the guard ring and the field plate.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: January 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroyuki Tanaka, Kota Ohi, Yuichi Onozawa, Yoshihiro Ikura, Kazutoshi Sugimura
  • Publication number: 20180190779
    Abstract: The position of the side wall of a metal electrode is precisely controlled and the coverage of a layer above the metal electrode is improved. A semiconductor device is provided, including: a semiconductor substrate; and a metal electrode formed above an upper surface of the semiconductor substrate, wherein a side wall of the metal electrode includes a lower portion contacting the semiconductor substrate, and an upper portion that is formed upper than the lower portion and has a smaller inclination relative to the upper surface of the semiconductor substrate than the lower portion. An active region formed in the semiconductor substrate is further included, and the metal electrode may be a field plate formed on an outer side relative to the active region on the upper surface of the semiconductor substrate. The upper portion of the side wall of the field plate may have an upward-convex shape.
    Type: Application
    Filed: February 20, 2018
    Publication date: July 5, 2018
    Inventors: Eri OGAWA, Yuichi ONOZAWA, Kazutoshi SUGIMURA, Hiroyuki TANAKA, Kota OHI, Yoshihiro IKURA
  • Publication number: 20170271440
    Abstract: Provided is a guard ring section to which a fine processing is easily applied. Provided is a semiconductor device comprising: a semiconductor substrate; an active region formed in the semiconductor substrate; and a guard ring section formed more outside than the active region in the semiconductor substrate, wherein the guard ring section includes: a guard ring formed in a circular pattern on an upper surface of the semiconductor substrate; an interlayer insulating film formed above the guard ring; a field plate formed in a circular pattern along the guard ring and above the interlayer insulating film; and a tungsten plug formed in a circular pattern along the guard ring and penetrating the interlayer insulating film to connect the guard ring and the field plate.
    Type: Application
    Filed: March 1, 2017
    Publication date: September 21, 2017
    Inventors: Hiroyuki TANAKA, Kota OHI, Yuichi ONOZAWA, Yoshihiro IKURA, Kazutoshi Sugimura
  • Patent number: 5972768
    Abstract: In a method of manufacturing a semiconductor device, an insulating film is formed on a surface of a p-type semiconductor region, and then removed from a selected portion of the p-type semiconductor region. An n-type region having a high concentration of arsenic atoms is formed in a surface layer of the selected portion of the p-type semiconductor region from which the insulating film is removed. Subsequently, boron ions are implanted over an entire surface of the device in a concentration that is lower than that of the n-type region and higher than that of the p-type semiconductor region, to a smaller depth than that of the n-type region, and heat treatment is then effected to form a high-concentration boron diffused region in a surface layer of the p-type semiconductor region.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: October 26, 1999
    Assignee: Fuji Electric Co. Ltd.
    Inventors: Yoshihiko Nagayasu, Tatsuhiko Fujihira, Kazutoshi Sugimura, Yoichi Ryokai
  • Patent number: 5869372
    Abstract: A semiconductor device manufacturing process is disclosed in which one processing step is reduced by replacing the photoresist film conventionally used for masking in the formation of the heavily doped n-type layer by an oxide film, and by monitoring, in the monitor region, the simultaneous formation of the contact holes in the oxide films different in the respective thickness thereof. An n+ region is formed by using a second insulation film and a polysilicon gate electrode formed on a semi-conductor wafer as masks for implanting arsenic ions. Further, a contact hole to be formed on a p-type region covered with a fourth insulation film and a second insulation film and a contact hole to be formed on the n+ region covered with the fourth insulation film are formed simultaneously under the monitoring of the formation of the contact holes in a monitor region.
    Type: Grant
    Filed: November 9, 1995
    Date of Patent: February 9, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tatsuhiko Fujihira, Seiji Momota, Takeyoshi Nishimura, Kazutoshi Sugimura, Masao Yoshino, Takashi Kobayashi