Abstract: The technology of the present disclosure improves an image quality in a solid-state imaging element that amplifies a voltage for every column. In the solid-state imaging element, an input transistor outputs, from a drain, an output voltage corresponding to a voltage between a source and a gate to which an input voltage is input. A base side current source transistor supplies a predetermined current from the drain of the input transistor to a base node determined in advance. A feedback circuit feeds back a part of the predetermined current to the gate of the input transistor. The clamp circuit limits the output voltage to a value higher than a lower limit voltage determined in advance.

Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

Abstract: A solid-state imaging device configured to suppress fixed pattern noise having column correlation and/or lateral correlation from being generated in images is disclosed. In one example, a solid-state imaging device includes unit pixels arranged in row and column directions, vertical signal lines respectively connected to at least one of the unit pixels arranged in the column direction, first converters connected to the respective vertical signal lines and configured to convert an analog pixel signal into a digital pixel signal in reading each unit pixel arranged in the row direction, an initialization voltage generator that outputs an initialization voltage for initializing the unit pixels or input nodes of the first converters, and an initialization voltage line that connects the initialization voltage generator and the first converters. The initialization voltage generator changes the initialization voltage that is output for each row and/or column to be processed by the first converters.

Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: An A/D converter and electronic equipment are disclosed. In one example, an A/D converter includes a comparator circuit and a first transistor. The comparator circuit compares a threshold voltage (Vth) to a pixel signal (SVSL). The first transistor has a control terminal and forms a clamp circuit, and receives an input of a result of the comparison. When the clamp circuit is turned on (closed), the first transistor equalizes currents flowing to a first predetermined position and a second predetermined position or equalizes voltages at the first predetermined position and the second predetermined position, the first predetermined position and the second predetermined position being connected to each other at the time of clamping. This makes it possible to suppress occurrence of streaking in a case where an excessive input is applied to a pixel signal line side.

Abstract: Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

Abstract: A solid-state imaging device configured to suppress fixed pattern noise having column correlation and/or lateral correlation from being generated in images is disclosed. In one example, a solid-state imaging device includes unit pixels arranged in row and column directions, vertical signal lines respectively connected to at least one of the unit pixels arranged in the column direction, first converters connected to the respective vertical signal lines and configured to convert an analog pixel signal into a digital pixel signal in reading each unit pixel arranged in the row direction, an initialization voltage generator that outputs an initialization voltage for initializing the unit pixels or input nodes of the first converters, and an initialization voltage line that connects the initialization voltage generator and the first converters. The initialization voltage generator changes the initialization voltage that is output for each row and/or column to be processed by the first converters.

Abstract: Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

Abstract: It is intended to improve reading speed of pixel signals in a solid-state imaging element provided with an ADC. A plurality of pixels are arrayed in a pixel block. A drive circuit drives the pixel block to output a plurality of pixel signals at the same time. A comparator successively selects the plurality of pixel signals and compares the selected pixel signals and a predetermined reference signal. A control section generates a control signal for updating the predetermined reference signal on the basis of comparison results of the comparator. A reference signal update section updates the predetermined reference signal according to the control signal.

Abstract: Noise is reduced in a circuit that converts voltage. A voltage conversion circuit includes a conversion transistor, a current source transistor, and a control circuit. In this voltage conversion circuit, the conversion transistor converts a potential of an input signal, the potential being changed from one of two different potentials to the other, by using predetermined current, and outputs the converted signal as an output signal. Furthermore, the current source transistor supplies the predetermined current. Then, in a case where the potential of the input signal is changed to the other potential, the control circuit stops supplying the predetermined current.

Abstract: The present technology relates to a controller, a control method, an AD converter, and an AD conversion method by which settling can be improved. The controller includes: a first current source that generates an output signal corresponding to an input signal; a second current source that supplies a current to charge a predetermined capacitance; and a control unit that controls the current supplied from the second current source to the predetermined capacitance, where the first current source and the second current source are each formed of a transistor. The controller further includes a supply unit that supplies a current flowing to the first current source and the second current source, where the current flowing to the first current source and the second current source is proportional to a current flowing in the supply unit. The present technology can be applied to an AD converter included in an imaging apparatus.

Abstract: A duty ratio correction circuit includes: a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal; a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction; a first capacitor; and a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal.

Abstract: A duty ratio correction circuit includes: a buffer circuit configured to generate a second signal based on a first signal, the second signal having a DC component corresponding to a first control signal; a waveform shaping section configured to shape a waveform of the second signal to generate a third signal that is a target of duty ratio correction; a first capacitor; and a first charge-discharge control circuit configured to selectively charge or discharge the first capacitor based on the third signal, to generate the first control signal.