Abstract: The present invention provides a dynamic circuit device that can prevent hardware and software from becoming larger in size and that can have smaller outside dimensions, less weight, and lower power consumption. For this purpose, the dynamic circuit device is provided with an operation instructing unit for instructing an operation and a cluster-layer wiring layer formed by disposing a plurality of cluster layers that include one or more lookup tables in which preset function elements are disposed and by connecting adjacent cluster layers with each other using cluster-layer connecting lines, wherein the dynamic circuit device changes the circuit configuration dynamically by changing operational states of the functional elements according to the instruction from the operation instructing unit.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: A description processing device has: a receiving unit which receives a behavior level description; a label-name generating unit which generates a label name; a label disposing unit which disposes a top label statement; an extracting unit which extracts an extracted label statement, a variable-name generating unit which generates a variable name; a replacing unit which replaces a statement immediately below the top label statement to the extracted label statement by a column of a conditional executable statement and an operation/assignment statement and replaces a jump statement for jumping to the extracted label statement by a column of an operation/assignment statement and a jump statement for jumping to the top label; a control unit which repeats the extraction, the generation of a new variable name, and the replacement; an inserting unit which inserts an operation/assignment statement; and an output unit which outputs the behavior level description.

Abstract: Disclosed is an automated synthesis system in which a generalized condition vector (GCV) is generated at a node that is the leaf of a tree indicating a conditional branch of a control/data flow graph representing the flow of behavioral control and data of a circuit. The GVC is a condition vector includes valid bits that are set as a condition vector of code 1 only at one component in a case where an outer conditional operation to a certain operation node is unresolved and, moreover, an inner conditional operation to said certain operation node is resolved, the valid bits being bits at positions where components of a vector of the inner side resolved conditional operation are 1's. The GVC of the operation node is calculated by taking a bitwise logical OR with the condition vector of the unresolved conditional operation.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: A receiving unit receiving a description expressing a finite state machine comprising states 0, 1, 2, . . . , N?1; a dividing unit dividing the states 0, 1, 2, . . . , N?1 into groups 0, 1, 2, . . . , M?1, wherein the dividing unit allocates the states 0, 1, . . . , L[0]?1 to the group 0, allocates the states L[0], L[0]+1, . . . , L[1]?1 to the group 1, allocates the states L[1], L[1]+1, . . . , L[2]?1 to the group 2, . . . , and allocates the states L[M?2], L[M?2]+1, . . . , L[M?1]?1=N?1 to the group M?1; and a generating unit generating a register transfer level description so that decoders which acquire the current state are generated for each group are provided.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: A description processing device has: a receiving unit which receives a behavior level description; a label-name generating unit which generates a label name; a label disposing unit which disposes a top label statement; an extracting unit which extracts an extracted label statement, a variable-name generating unit which generates a variable name; a replacing unit which replaces a statement immediately below the top label statement to the extracted label statement by a column of a conditional executable statement and an operation/assignment statement and replaces a jump statement for jumping the extracted label statement by a column of an operation/assignment statement and a jump statement for jumping to the top label; a control unit which repeats the extraction, the generation of a new variable name, and the replacement; an inserting unit which inserts an operation/assignment statement; and an output unit which outputs the behavior level description.

Abstract: A receiving unit 20 receiving a description expressing a finite state machine comprising states 0, 1, 2, . . . , N?1; a dividing unit 30 dividing the states 0, 1, 2, . . . , N?1 into groups 0, 1, 2, . . . , M?1, wherein the dividing unit allocates the states 0, 1, . . . , L[0]?1 to the group 0, allocates the states L[0], L[0]+1, . . . , L[1]?1 to the group 1, allocates the states L[1], L[1]+1, . . . , L[2]?1 to the group 2, . . . , and allocates the states L[M?2], L[M?2]+1, . . . , L[M?1]?1=N?1 to the group M?1, and a generating unit 40 generating a register transfer level description so that decoders which acquire the current state are generated for each group are provided.

Abstract: Disclosed is a behavioral synthesis apparatus for generating a test bench where the same test vector can be used in both the behavioral simulation and the RTL simulation. The apparatus includes input application/output signal observation timing signal generation means that generates an input application timing signal, an output observation timing signal, and logic circuits for the input application timing signal and the output observation timing signal; and test bench generation means that generates a test bench that observes the signals, applies inputs, and observes outputs.

Abstract: Disclosed is an automated synthesis system in which a generalized condition vector (GCV) is generated at a node that is the leaf of a tree indicating a conditional branch of a control/data flow graph representing the flow of behavioral control and data of a circuit. The GVC is a condition vector includes valid bits that are set as a condition vector of code 1 only at one component in a case where an outer conditional operation to a certain operation node is unresolved and, moreover, an inner conditional operation to said certain operation node is resolved, the valid bits being bits at positions where components of a vector of the inner side resolved conditional operation are 1's. The GVC of the operation node is calculated by taking a bitwise logical OR with the condition vector of the unresolved conditional operation.

Abstract: An apparatus for automatically preparing a bus interface preparation apparatus is provided which is capable of preventing duplication of addresses of registers and memories. When data of a hardware description 10 are input into the extracting portion 101, the extracting portion 101 extracts from the data whether the memory element is a memory device or an FF. The extracting portion 101 reads the top address and the address size of the memory element when the memory is the memory element and reads address when the memory is an FF, and the thus read data are output to the address competition detecting portion 103. The address competition detecting portion 103 detects competition of the addresses by determining whether the address information stored in the bit data memory portion 102 includes 1. The output portion 104 converts the data concerning address of the memory into a description language of the hardware of the bus interface circuit.

Abstract: The system synthesizer of the present invention is provided for synthesizing a system containing from a system description, the system description containing a permanent connection statement describing an access from a first circuit to a memory element in an interface circuit, and a behavioral sequential operation statement describing the operation of a second circuit which contains an access from the second circuit to the memory element in the interface circuit.