Abstract: A microcomputer includes a central processing unit (CPU) and an electrically erasable and programmable nonvolatile memory (EEPROM) fabricated on a single semiconductor chip. When CPU issues a data write request to EEPROM, a data write control circuit is initiated to perform a data write-processing in which data in an address of EEPROM selected by CPU is first erased and thereafter data from CPU is written into that selected address. There is further provided an over-written detection circuit for detecting that CPU issues another data write request to EEPROM while the data write control circuit is performing the data write-processing and for producing an over-write detection signal to CPU.

Abstract: A transmitting data processor comprises a data processing unit for supplying a predetermined length of data to be transferred and generating a transfer start signal, and a data transferring unit receiving the predetermined length of data to be transferred from the data processing unit and for transferring the predetermined length of data in a serial form to a receiving data processor. The transmitting data processor also includes a busy detector for detecting a busy signal from the receiving data processor, a register for temporarily holding the transfer start signal from the data processing unit, and a start controller associated to the data transferring unit for causing the data transferring unit to stop the transfer of data during the period the busy signal is active and for allowing the data transferring unit to start the transfer of data when the busy signal becomes inactive after the transfer start signal is generated.

Abstract: A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.