Abstract: A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to a startup circuit of a switching-mode power supply, the multipurpose resistor serves as startup resistor for limiting the flow of rush current during the startup period of the switching-mode power supply.

Abstract: A semiconductor device comprises a P?-type semiconductor substrate (15), an N?-type semiconductor substrate (21) formed on the P?-type semiconductor substrate (15), an upper P-type semiconductor region (13) formed in the surface region of the N?-type semiconductor substrate (21) and electrically connected to a ground electrode (1), a lower P-type semiconductor region (14) formed beneath the upper P-type semiconductor region (13), a first N+-type semiconductor region (22) electrically connected to a drain electrode (2), a P-type semiconductor region (19) functioning as a channel forming region, a P+-semiconductor region (12) electrically connected to a back gate electrode (5), a second N+-semiconductor region (23) electrically connected to a source electrode (4), and a gate electrode (3) and a gate insulating film (31) both on the P-type semiconductor region (19), and the lower P-type semiconductor region (14) extends toward the first N+-type semiconductor region (22).

Abstract: A voltage measurement device includes: a charging circuit 100 having a first switch group of semiconductor elements P1, P2 for connecting voltages of respective blocks, into which a plurality of voltage sources VCn are divided, to a charging condenser Cn and a second switch groups of semiconductor elements N3, N4 for connecting the voltage of each block accumulated in the charging condenser Cn to an output terminal; an A/D converter 120 connected to an output terminal of the charging circuit 100; and a CPU 130 measuring a stray capacitance including a parasitic capacitance of the semiconductor element N4 in advance and further calculates an error voltage due to electrical charges accumulated in the parasitic capacitance. The CPU 130 further calculates a true value of the voltage of each block by subtracting the error voltage from a measured value of terminal voltage at the output terminal of the charging circuit 100.

Abstract: A composite integrated circuit incorporating two LDMOSFETs of unlike designs, with the consequent creation of a parasitic transistor. A multipurpose resistor is integrally built into the composite integrated circuit in order to prevent the parasitic transistor from accidentally turning on. In an intended application of the composite integrated circuit to a startup circuit of a switching-mode power supply, the multipurpose resistor serves as startup resistor for limiting the flow of rush current during the startup period of the switching-mode power supply.

Abstract: A semiconductor device comprises a P?-type semiconductor substrate (15), an N?-type semiconductor substrate (21) formed on the P?-type semiconductor substrate (15), an upper P-type semiconductor region (13) formed in the surface region of the N?-type semiconductor substrate (21) and electrically connected to a ground electrode (1), a lower P-type semiconductor region (14) formed beneath the upper P-type semiconductor region (13), a first N+-type semiconductor region (22) electrically connected to a drain electrode (2), a P-type semiconductor region (19) functioning as a channel forming region, a P+-semiconductor region (12) electrically connected to a back gate electrode (5), a second N+-semiconductor region (23) electrically connected to a source electrode (4), and a gate electrode (3) and a gate insulating film (31) both on the P-type semiconductor region (19), and the lower P-type semiconductor region (14) extends toward the first N+-type semiconductor region (22).

Abstract: A voltage measurement device includes a first group of switches Q1, Q2, a second group of switches Q7, Q8 and a third groups of switches Q5, Q6. By turning on the third group of switches Q5, Q6, the first group of switches Q1, Q2 are turned on, so that a condenser C1 is charged by voltage impressed between a voltage input terminal A and a voltage input terminal B. While the first group of switches Q1, Q2 are turned off by tuning off the third group of switches Q5, Q6, the second group of switches Q7, Q8 are turned on, so that voltage retained in the condenser C1 is generated between a voltage output terminal G and a voltage output terminal H.

Abstract: A voltage measurement device includes a first group of switches Q1, Q2, a second group of switches Q7, Q8 and a third groups of switches Q5, Q6. By turning on the third group of switches Q5, Q6, the first group of switches Q1, Q2 are turned on, so that a condenser C1 is charged by voltage impressed between a voltage input terminal A and a voltage input terminal B. While the first group of switches Q1, Q2 are turned off by tuning off the third group of switches Q5, Q6, the second group of switches Q7, Q8 are turned on, so that voltage retained in the condenser C1 is generated between a voltage output terminal G and a voltage output terminal H.

Abstract: A voltage measurement device includes: a charging circuit 100 having a first switch group of semiconductor elements P1, P2 for connecting voltages of respective blocks, into which a plurality of voltage sources VCn are divided, to a charging condenser Cn and a second switch groups of semiconductor elements N3, N4 for connecting the voltage of each block accumulated in the charging condenser Cn to an output terminal; an A/D converter 120 connected to an output terminal of the charging circuit 100; and a CPU 130 measuring a stray capacitance including a parasitic capacitance of the semiconductor element N4 in advance and further calculates an error voltage due to electrical charges accumulated in the parasitic capacitance. The CPU 130 further calculates a true value of the voltage of each block by subtracting the error voltage from a measured value of terminal voltage at the output terminal of the charging circuit 100.

Abstract: The voltage measuring apparatus includes a voltage measuring unit 2 being connected to a battery 1, a voltage converting unit 3 connected to the voltage measuring unit 2, and a controller 4 which controls the operation of the voltage measuring unit 2 based on output of the voltage converting unit 3. The voltage measuring unit 2 includes Pch-MOSFET elements P1 and P2 constituting a first switch group connected to both terminals of a voltage source Vcn in the battery 1, a capacitor Cn connected between the elements P1 and P2, and Nch-MOSFET elements N3 and N4 constituting a second switch group connected to both terminals of the capacitor Cn and to both terminals of the voltage output terminal. A source and a back gate of the Nch-MOSFET element N3 of the second switch group are connected to each other.

Abstract: The voltage measuring apparatus includes a voltage measuring unit 2 being connected to a battery 1, a voltage converting unit 3 connected to the voltage measuring unit 2, and a controller 4 which controls the operation of the voltage measuring unit 2 based on output of the voltage converting unit 3. The voltage measuring unit 2 includes Pch-MOSFET elements P1 and P2 constituting a first switch group connected to both terminals of a voltage source Vcn in the battery 1 , a capacitor Cn connected between the elements P1 and P2, and Nch-MOSFET elements N3 and N4 constituting a second switch group connected to both terminals of the capacitor Cn and to both terminals of the voltage output terminal. A source and a back gate of the Nch-MOSFET element N3 of the second switch group are connected to each other.