Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

Abstract: A data processing apparatus (1) can implement the execution of a virtual machine instruction based on an execution routine specified by the native instruction of a CPU (2) and has an address converting unit (3) capable of sequentially converting an address output from the CPU into the address of the native instruction by utilizing the address of a prepared execution routine in response to the application of a prescribed condition. The address converting unit reads a virtual machine instruction to be executed next and prepares the address of an execution routine corresponding thereto in parallel with the execution of the execution routine by the CPU based on the address of the native instruction which is sequentially converted. Accordingly, it is possible to reduce the overhead of a processing of loading the virtual machine instruction and a processing of executing an instruction in accordance with the execution routine which is caused by an address calculation processing based on the load processing.

Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

Abstract: A data processor of the present invention efficiently performs decision processing on register conflict. The data processor contains n-bit instructions and 2n-bit instructions in an instruction set and includes an instruction control unit that can decide whether registers specified in register specification fields of the instructions conflict between the instructions. The 2n-bit instructions including register specification fields have the register specification fields in the first half n bits thereof, and the register specification fields in the first half n bits comprise the same placement as register specification fields in the n-bit instructions. Shift operations required to cut out the register specification fields from the instructions, either 2n-bit or n-bit instructions, can be simplified or deleted by aligning the register specification fields in the 2n-bit instructions with those in the n-bit instructions.