Patents by Inventor Kazuya Horie

Kazuya Horie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10490419
    Abstract: In manufacturing a trench type MOSFET, reliability of a semiconductor device is prevented from being degraded due to a short circuit or lowering of withstand voltage between a trench gate electrode and a source region. To achieve the above, poly-silicon films are formed inside a trench in a main surface of a semiconductor substrate and over the semiconductor substrate. Further, phosphorus is thermally diffused into each poly-silicon film from a phosphorous film over an upper surface of the poly-silicon film. Still further, a silicon oxide film formed in a surface layer of the poly-silicon film by the thermal diffusion process is removed by a first dry etching process using a fluorocarbon gas or a hydroxy-fluorocarbon gas. Then, by performing a second dry etching process using a Cl2 gas etc., an insulating film is exposed and, thereby, a trench gate electrode including the poly-silicon film is formed.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: November 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuya Horie, Katsuhiro Uchimura, Kazuhiro Toi, Masakazu Nakano
  • Patent number: 10414020
    Abstract: [Problem] To provide a grindstone and a grinding/polishing device using same with which, in addition to it being possible to perform the three processes of rough processing, lapping, and polishing with the same device: double-sided processing is also possible; processing rate does not decrease even when used continuously; and dressing can be omitted. [Solution] A grindstone for grinding/polishing workpieces, the grindstone being characterized in comprising multiple grindstone pillars, which are obtained from a binding agents and abrasive grains for grinding/polishing the workpieces and disposed in parallel with an axis (L) in the depth direction of the grinding/polishing surface, and the grindstone matrix integrally formed with the grindstone pillars, and a grinding/polishing device using said grindstone.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 17, 2019
    Assignee: NANO TEM CO., LTD.
    Inventors: Atsushi Takada, Masakazu Takatsu, Kyosuke Ohashi, Kazuya Horie, Kozo Ishizaki
  • Publication number: 20180068856
    Abstract: In manufacturing a trench type MOSFET, reliability of a semiconductor device is prevented from being degraded due to a short circuit or lowering of withstand voltage between a trench gate electrode and a source region. To achieve the above, poly-silicon films are formed inside a trench in a main surface of a semiconductor substrate and over the semiconductor substrate. Further, phosphorus is thermally diffused into each poly-silicon film from a phosphorous film over an upper surface of the poly-silicon film. Still further, a silicon oxide film formed in a surface layer of the poly-silicon film by the thermal diffusion process is removed by a first dry etching process using a fluorocarbon gas or a hydroxy-fluorocarbon gas. Then, by performing a second dry etching process using a Cl2 gas etc., an insulating film is exposed and, thereby, a trench gate electrode including the poly-silicon film is formed.
    Type: Application
    Filed: July 6, 2017
    Publication date: March 8, 2018
    Inventors: Kazuya HORIE, Katsuhiro UCHIMURA, Kazuhiro TOI, Masakazu NAKANO
  • Publication number: 20150258656
    Abstract: [Problem] To provide a grindstone and a grinding/polishing device using same with which, in addition to it being possible to perform the three processes of rough processing, lapping, and polishing with the same device: double-sided processing is also possible; processing rate does not decrease even when used continuously; and dressing can be omitted. [Solution] A grindstone for grinding/polishing workpieces, the grindstone being characterized in comprising multiple grindstone pillars, which are obtained from a binding agents and abrasive grains for grinding/polishing the workpieces and disposed in parallel with an axis (L) in the depth direction of the grinding/polishing surface, and the grindstone matrix integrally formed with the grindstone pillars, and a grinding/polishing device using said grindstone.
    Type: Application
    Filed: September 27, 2013
    Publication date: September 17, 2015
    Applicant: NANO TEM CO., LTD.
    Inventors: Atsushi Takada, Masakazu Takatsu, Kyosuke Ohashi, Kazuya Horie, Kozo Ishizaki
  • Patent number: 8710619
    Abstract: To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 ?m. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Kawamata, Atsushi Tachigami, Kazuya Horie, Tatsuya Shiromoto, Tetsuya Nitta, Hironori Shimizu
  • Publication number: 20120049318
    Abstract: To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 ?m. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.
    Type: Application
    Filed: August 11, 2011
    Publication date: March 1, 2012
    Inventors: Tatsuya Kawamata, Atsushi Tachigami, Kazuya Horie, Tatsuya Shiromoto, Tetsuya Nitta, Hironori Shimizu