Abstract: A method for designing a fault detection circuit includes an extraction step of selecting a fixed signal value based on an index, and extracting, by using the fixed signal value selected, one or some but not all of three-signal implication relationships.

Abstract: A filp-flop circuit includes master latch including a first inverter and a first tri-state inverter, wherein the first tri-state inverter includes a first NMOS transistor and a first PMOS transistor; a slave latch including a second inverter and a second tri-state inverter, wherein the second tri-state inverter includes a second PMOS transistor and a second NMOS transistor; and at least one of a first wiring configured to connect a source of the first PMOS transistor and a source of the first NMOS transistor and a second wiring configured to connect a source of the second PMOS transistor and a source of the second NMOS transistor.

Abstract: Disclosed is a data storage circuit that stores target input data inputted to a data input terminal and outputs the stored data as target output data through a data output terminal. The data storage circuit includes a clock control circuit that outputs a master clock signal and a slave clock signal based on a reference clock signal, a master latch circuit that takes the target input data based on the master clock signal, holds the taken data, and outputs the taken data as master output data, a slave latch circuit that takes the master output data based on the slave clock signal, holds the taken data, and outputs the taken data as slave output data, and an output data generation circuit that generates the target output data.

Abstract: Disclosed is a flip flop circuit including a master latch circuit receiving master input data based on target input data, a slave latch circuit configured to load master output data from the master latch circuit and to hold the master output data, and a data output section, target output data based on the target input data being output from the data output section. The slave latch circuit includes a first to an N-th slave latch circuits provided in parallel with the master latch circuit (N is an integer of 2 or larger), the flip flop circuit further includes an output selection circuit selecting any one of data output from the first to N-th slave latch circuits, and selection data from the output selection circuit is output from the data output section as the target output data.

Abstract: Disclosed is a data storage circuit that stores target input data inputted to a data input terminal and outputs the stored data as target output data through a data output terminal. The data storage circuit includes a clock control circuit that outputs a master clock signal and a slave clock signal based on a reference clock signal, a master latch circuit that takes the target input data based on the master clock signal, holds the taken data, and outputs the taken data as master output data, a slave latch circuit that takes the master output data based on the slave clock signal, holds the taken data, and outputs the taken data as slave output data, and an output data generation circuit that generates the target output data.

Abstract: Disclosed is a flip flop circuit including a master latch circuit receiving master input data based on target input data, a slave latch circuit configured to load master output data from the master latch circuit and to hold the master output data, and a data output section, target output data based on the target input data being output from the data output section. The slave latch circuit includes a first to an N-th slave latch circuits provided in parallel with the master latch circuit (N is an integer of 2 or larger), the flip flop circuit further includes an output selection circuit selecting any one of data output from the first to N-th slave latch circuits, and selection data from the output selection circuit is output from the data output section as the target output data.

Abstract: In order to integrate two FIFOs such as a transmitting FIFO and a receiving FIFO into one FIFO so that a memory area is effectively used, a FIFO memory device 10 comprises a transmitting FIFO control section 20 for writing transmission input data to a memory 100 and outputting the transmitted data written to the memory 100 in order of the data inputting, a receiving FIFO control section 30 for writing receipt input data to the memory 100 and outputting the received data written to the memory 100 in order of the data inputting, a first pointer register 26 for storing the write address of the transmitted data or the read address of the transmission input data in the memory 100, and a second pointer register 36 for storing the write address of the receipt input data or the read address of the receipt output data in the memory 100.

Abstract: A method and apparatus are described for controlling a phase of the data window, using data patterns in addition to any dedicated sync patterns to improve the synchronization when decoding data from a magnetic recording medium, such as, for example, a floppy diskette. A data window is generated to separate the data pulses from the clock pulses in a pulse series which has been recorded using a method which generates peak shifts such as MFM (Multi-Frequency Modulation) or FM. When a pulse series that matches any of a set of predetermined bit patterns is found in the data, the phase of the data window signal is adjusted based on the deviation of the timing of a selected transition in the pattern from the expected ideal value. Preferably the bit patterns have a plurality of symmetrically arranged bits and include a criterion position that is not affected by a peak shift. The pulse series from the recording medium is separated into data pulses and clock pulses by using the adjusted data window.